0068-target-riscv-rvv-1.0-floating-point-integer-type-con.patch 7.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160
  1. From 368a058ec5f3f608f60280ac0f0c6c876725d62c Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Wed, 5 Aug 2020 14:31:00 +0800
  4. Subject: [PATCH 068/107] target/riscv: rvv-1.0: floating-point/integer
  5. type-convert instructions
  6. Add the following instructions:
  7. * vfcvt.rtz.xu.f.v
  8. * vfcvt.rtz.x.f.v
  9. Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
  10. modes.
  11. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  12. ---
  13. target/riscv/insn32.decode | 11 ++--
  14. target/riscv/insn_trans/trans_rvv.c.inc | 83 ++++++++++++++++---------
  15. 2 files changed, 59 insertions(+), 35 deletions(-)
  16. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  17. index 8794397c74..c3482a5f44 100644
  18. --- a/target/riscv/insn32.decode
  19. +++ b/target/riscv/insn32.decode
  20. @@ -560,10 +560,13 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
  21. vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
  22. vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
  23. vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
  24. -vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
  25. -vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
  26. -vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
  27. -vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
  28. +
  29. +vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
  30. +vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
  31. +vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
  32. +vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
  33. +vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
  34. +vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
  35. vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
  36. vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
  37. vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
  38. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  39. index 92f66728c6..86eefbf87b 100644
  40. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  41. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  42. @@ -1,5 +1,4 @@
  43. /*
  44. - * RISC-V translation routines for the RVV Standard Extension.
  45. *
  46. * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
  47. *
  48. @@ -2600,33 +2599,41 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
  49. vext_check_ss(s, a->rd, a->rs2, a->vm);
  50. }
  51. -#define GEN_OPFV_TRANS(NAME, CHECK) \
  52. -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  53. -{ \
  54. - if (CHECK(s, a)) { \
  55. - uint32_t data = 0; \
  56. - static gen_helper_gvec_3_ptr * const fns[3] = { \
  57. - gen_helper_##NAME##_h, \
  58. - gen_helper_##NAME##_w, \
  59. - gen_helper_##NAME##_d, \
  60. - }; \
  61. - TCGLabel *over = gen_new_label(); \
  62. - gen_set_rm(s, RISCV_FRM_DYN); \
  63. - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
  64. - \
  65. - data = FIELD_DP32(data, VDATA, VM, a->vm); \
  66. - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
  67. - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  68. - vreg_ofs(s, a->rs2), cpu_env, 0, \
  69. - s->vlen / 8, data, fns[s->sew - 1]); \
  70. - mark_vs_dirty(s); \
  71. - gen_set_label(over); \
  72. - return true; \
  73. - } \
  74. - return false; \
  75. +static bool do_opfv(DisasContext *s, arg_rmr *a,
  76. + gen_helper_gvec_3_ptr *fn,
  77. + bool (*checkfn)(DisasContext *, arg_rmr *),
  78. + int rm)
  79. +{
  80. + if (checkfn(s, a)) {
  81. + uint32_t data = 0;
  82. + TCGLabel *over = gen_new_label();
  83. + gen_set_rm(s, rm);
  84. + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
  85. +
  86. + data = FIELD_DP32(data, VDATA, VM, a->vm);
  87. + data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  88. + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  89. + vreg_ofs(s, a->rs2), cpu_env, 0,
  90. + s->vlen / 8, data, fn);
  91. + mark_vs_dirty(s);
  92. + gen_set_label(over);
  93. + return true;
  94. + }
  95. + return false;
  96. +}
  97. +
  98. +#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \
  99. +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  100. +{ \
  101. + static gen_helper_gvec_3_ptr * const fns[3] = { \
  102. + gen_helper_##NAME##_h, \
  103. + gen_helper_##NAME##_w, \
  104. + gen_helper_##NAME##_d \
  105. + }; \
  106. + return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM); \
  107. }
  108. -GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
  109. +GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
  110. /* Vector Floating-Point MIN/MAX Instructions */
  111. GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
  112. @@ -2672,7 +2679,7 @@ GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
  113. GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
  114. /* Vector Floating-Point Classify Instruction */
  115. -GEN_OPFV_TRANS(vfclass_v, opfv_check)
  116. +GEN_OPFV_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN)
  117. /* Vector Floating-Point Merge Instruction */
  118. GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
  119. @@ -2727,10 +2734,24 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
  120. }
  121. /* Single-Width Floating-Point/Integer Type-Convert Instructions */
  122. -GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
  123. -GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
  124. -GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
  125. -GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
  126. +#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \
  127. +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  128. +{ \
  129. + static gen_helper_gvec_3_ptr * const fns[3] = { \
  130. + gen_helper_##HELPER##_h, \
  131. + gen_helper_##HELPER##_w, \
  132. + gen_helper_##HELPER##_d \
  133. + }; \
  134. + return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM); \
  135. +}
  136. +
  137. +GEN_OPFV_CVT_TRANS(vfcvt_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_DYN)
  138. +GEN_OPFV_CVT_TRANS(vfcvt_x_f_v, vfcvt_x_f_v, RISCV_FRM_DYN)
  139. +GEN_OPFV_CVT_TRANS(vfcvt_f_xu_v, vfcvt_f_xu_v, RISCV_FRM_DYN)
  140. +GEN_OPFV_CVT_TRANS(vfcvt_f_x_v, vfcvt_f_x_v, RISCV_FRM_DYN)
  141. +/* Reuse the helper functions from vfcvt.xu.f.v and vfcvt.x.f.v */
  142. +GEN_OPFV_CVT_TRANS(vfcvt_rtz_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_RTZ)
  143. +GEN_OPFV_CVT_TRANS(vfcvt_rtz_x_f_v, vfcvt_x_f_v, RISCV_FRM_RTZ)
  144. /* Widening Floating-Point/Integer Type-Convert Instructions */
  145. --
  146. 2.33.1