0010-target-riscv-rvb-modified-srow-error.patch 2.0 KB

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  1. From 98a9115f2667b9d029fd83da50c42c15d5e40bd6 Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Tue, 13 Jul 2021 13:15:23 +0800
  4. Subject: [PATCH 10/11] target/riscv: rvb: modified srow error
  5. srow rd, rs1, rs2
  6. modified the error when rs1 >= 0xffffffff
  7. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  8. ---
  9. target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
  10. target/riscv/translate.c | 20 ++++++++++++++++++++
  11. 2 files changed, 22 insertions(+), 2 deletions(-)
  12. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  13. index fde91c1953..307fb982e0 100644
  14. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  15. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  16. @@ -547,14 +547,14 @@ static bool trans_srow(DisasContext *ctx, arg_srow *a)
  17. {
  18. REQUIRE_64BIT(ctx);
  19. REQUIRE_EXT(ctx, RVB);
  20. - return gen_shiftw(ctx, a, gen_sro);
  21. + return gen_shiftw(ctx, a, gen_srow);
  22. }
  23. static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
  24. {
  25. REQUIRE_64BIT(ctx);
  26. REQUIRE_EXT(ctx, RVB);
  27. - return gen_shiftiw(ctx, a, gen_sro);
  28. + return gen_shiftiw(ctx, a, gen_srow);
  29. }
  30. static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  31. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  32. index 79d93feec3..4d713b16e0 100644
  33. --- a/target/riscv/translate.c
  34. +++ b/target/riscv/translate.c
  35. @@ -627,6 +627,26 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
  36. tcg_gen_not_tl(ret, ret);
  37. }
  38. +static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2)
  39. +{
  40. + TCGv_i32 t1 = tcg_temp_new_i32();
  41. + TCGv_i32 t2 = tcg_temp_new_i32();
  42. +
  43. + /* truncate to 32-bits */
  44. + tcg_gen_trunc_tl_i32(t1, arg1);
  45. + tcg_gen_trunc_tl_i32(t2, arg2);
  46. +
  47. + tcg_gen_not_i32(t1, t1);
  48. + tcg_gen_shr_i32(t1, t1, t2);
  49. + tcg_gen_not_i32(t1, t1);
  50. +
  51. + /* sign-extend 64-bits */
  52. + tcg_gen_ext_i32_tl(ret, t1);
  53. +
  54. + tcg_temp_free_i32(t1);
  55. + tcg_temp_free_i32(t2);
  56. +}
  57. +
  58. static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
  59. {
  60. TCGv source1 = tcg_temp_new();
  61. --
  62. 2.33.0