0005-Upgrade-CLINT-implementation-to-ACLINT-and-Misc.patch 13 KB

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  1. From c38ef2e5f9e957df5d01fe8afb0c6ace1178c322 Mon Sep 17 00:00:00 2001
  2. From: "demin.han" <demin.han@starfivetech.com>
  3. Date: Mon, 27 Feb 2023 13:49:17 +0800
  4. Subject: [PATCH 5/6] Upgrade CLINT implementation to ACLINT and Misc
  5. ---
  6. hw/riscv/Kconfig | 4 +-
  7. hw/riscv/starfive_u.c | 105 ++++++++++++++++++------------------------
  8. 2 files changed, 46 insertions(+), 63 deletions(-)
  9. diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
  10. index 369495f2fe..5e95cf4875 100644
  11. --- a/hw/riscv/Kconfig
  12. +++ b/hw/riscv/Kconfig
  13. @@ -90,7 +90,7 @@ config STARFIVE_U
  14. bool
  15. select CADENCE
  16. select MSI_NONBROKEN
  17. - select SIFIVE_CLINT
  18. + select RISCV_ACLINT
  19. select SIFIVE_GPIO
  20. select SIFIVE_PDMA
  21. select SIFIVE_PLIC
  22. @@ -100,4 +100,4 @@ config STARFIVE_U
  23. select SIFIVE_U_PRCI
  24. select SSI_M25P80
  25. select SSI_SD
  26. - select UNIMP
  27. \ No newline at end of file
  28. + select UNIMP
  29. diff --git a/hw/riscv/starfive_u.c b/hw/riscv/starfive_u.c
  30. index c8e27ab805..0a143a59cf 100644
  31. --- a/hw/riscv/starfive_u.c
  32. +++ b/hw/riscv/starfive_u.c
  33. @@ -35,7 +35,6 @@
  34. */
  35. #include "qemu/osdep.h"
  36. -#include "qemu/log.h"
  37. #include "qemu/error-report.h"
  38. #include "qapi/error.h"
  39. #include "qapi/visitor.h"
  40. @@ -52,18 +51,19 @@
  41. #include "hw/riscv/starfive_u.h"
  42. #include "hw/riscv/boot.h"
  43. #include "hw/char/sifive_uart.h"
  44. -#include "hw/intc/sifive_clint.h"
  45. +#include "hw/intc/riscv_aclint.h"
  46. #include "hw/intc/sifive_plic.h"
  47. #include "hw/misc/sifive_test.h"
  48. #include "chardev/char.h"
  49. #include "net/eth.h"
  50. -#include "sysemu/arch_init.h"
  51. #include "sysemu/device_tree.h"
  52. #include "sysemu/runstate.h"
  53. #include "sysemu/sysemu.h"
  54. #include <libfdt.h>
  55. +/* CLINT timebase frequency */
  56. +#define CLINT_TIMEBASE_FREQ 1000000
  57. static const MemMapEntry starfive_u_memmap[] = {
  58. [STARFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
  59. [STARFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
  60. @@ -98,9 +98,15 @@ static void create_fdt(StarFiveUState *s, const MemMapEntry *memmap,
  61. int cpu;
  62. uint32_t *cells;
  63. char *nodename;
  64. - char ethclk_names[] = "pclk\0hclk";
  65. uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
  66. uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
  67. + static const char * const ethclk_names[2] = { "pclk", "hclk" };
  68. + static const char * const clint_compat[2] = {
  69. + "sifive,clint0", "riscv,clint0"
  70. + };
  71. + static const char * const plic_compat[2] = {
  72. + "sifive,plic-1.0.0", "riscv,plic0"
  73. + };
  74. if (ms->dtb) {
  75. fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
  76. @@ -162,7 +168,7 @@ static void create_fdt(StarFiveUState *s, const MemMapEntry *memmap,
  77. qemu_fdt_add_subnode(fdt, "/cpus");
  78. qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
  79. - SIFIVE_CLINT_TIMEBASE_FREQ);
  80. + CLINT_TIMEBASE_FREQ);
  81. qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
  82. qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
  83. @@ -212,7 +218,8 @@ static void create_fdt(StarFiveUState *s, const MemMapEntry *memmap,
  84. nodename = g_strdup_printf("/soc/clint@%lx",
  85. (long)memmap[STARFIVE_U_DEV_CLINT].base);
  86. qemu_fdt_add_subnode(fdt, nodename);
  87. - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
  88. + qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
  89. + (char **)&clint_compat, ARRAY_SIZE(clint_compat));
  90. qemu_fdt_setprop_cells(fdt, nodename, "reg",
  91. 0x0, memmap[STARFIVE_U_DEV_CLINT].base,
  92. 0x0, memmap[STARFIVE_U_DEV_CLINT].size);
  93. @@ -269,7 +276,8 @@ static void create_fdt(StarFiveUState *s, const MemMapEntry *memmap,
  94. (long)memmap[STARFIVE_U_DEV_PLIC].base);
  95. qemu_fdt_add_subnode(fdt, nodename);
  96. qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
  97. - qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
  98. + qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
  99. + (char **)&plic_compat, ARRAY_SIZE(plic_compat));
  100. qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
  101. qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
  102. cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
  103. @@ -415,8 +423,8 @@ static void create_fdt(StarFiveUState *s, const MemMapEntry *memmap,
  104. qemu_fdt_setprop_cell(fdt, nodename, "interrupts", STARFIVE_U_GEM_IRQ);
  105. qemu_fdt_setprop_cells(fdt, nodename, "clocks",
  106. prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
  107. - qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
  108. - sizeof(ethclk_names));
  109. + qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
  110. + (char **)&ethclk_names, ARRAY_SIZE(ethclk_names));
  111. qemu_fdt_setprop(fdt, nodename, "local-mac-address",
  112. s->soc.gem.conf.macaddr.a, ETH_ALEN);
  113. qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
  114. @@ -468,7 +476,7 @@ static void create_fdt(StarFiveUState *s, const MemMapEntry *memmap,
  115. g_free(nodename);
  116. update_bootargs:
  117. - if (cmdline) {
  118. + if (cmdline && *cmdline) {
  119. qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
  120. }
  121. }
  122. @@ -486,7 +494,6 @@ static void starfive_u_machine_init(MachineState *machine)
  123. const MemMapEntry *memmap = starfive_u_memmap;
  124. StarFiveUState *s = RISCV_U_MACHINE(machine);
  125. MemoryRegion *system_memory = get_system_memory();
  126. - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
  127. MemoryRegion *flash0 = g_new(MemoryRegion, 1);
  128. target_ulong start_addr = memmap[STARFIVE_U_DEV_DRAM].base;
  129. target_ulong firmware_end_addr, kernel_start_addr;
  130. @@ -504,13 +511,11 @@ static void starfive_u_machine_init(MachineState *machine)
  131. &error_abort);
  132. object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
  133. &error_abort);
  134. - qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
  135. + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
  136. /* register RAM */
  137. - memory_region_init_ram(main_mem, NULL, "riscv.starfive.u.ram",
  138. - machine->ram_size, &error_fatal);
  139. memory_region_add_subregion(system_memory, memmap[STARFIVE_U_DEV_DRAM].base,
  140. - main_mem);
  141. + machine->ram);
  142. /* register QSPI0 Flash */
  143. memory_region_init_ram(flash0, NULL, "riscv.starfive.u.flash0",
  144. @@ -555,12 +560,10 @@ static void starfive_u_machine_init(MachineState *machine)
  145. if (riscv_is_32bit(&s->soc.u_cpus)) {
  146. firmware_end_addr = riscv_find_and_load_firmware(machine,
  147. - "opensbi-riscv32-generic-fw_dynamic.bin",
  148. - start_addr, NULL);
  149. + RISCV32_BIOS_BIN, start_addr, NULL);
  150. } else {
  151. firmware_end_addr = riscv_find_and_load_firmware(machine,
  152. - "opensbi-riscv64-generic-fw_dynamic.bin",
  153. - start_addr, NULL);
  154. + RISCV64_BIOS_BIN, start_addr, NULL);
  155. }
  156. if (machine->kernel_filename) {
  157. @@ -595,11 +598,14 @@ static void starfive_u_machine_init(MachineState *machine)
  158. start_addr_hi32 = (uint64_t)start_addr >> 32;
  159. }
  160. + /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
  161. + machine->fdt = s->fdt;
  162. +
  163. /* reset vector */
  164. - uint32_t reset_vec[11] = {
  165. + uint32_t reset_vec[12] = {
  166. s->msel, /* MSEL pin state */
  167. 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
  168. - 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
  169. + 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
  170. 0xf1402573, /* csrr a0, mhartid */
  171. 0,
  172. 0,
  173. @@ -607,6 +613,7 @@ static void starfive_u_machine_init(MachineState *machine)
  174. start_addr, /* start: .dword */
  175. start_addr_hi32,
  176. fdt_load_addr, /* fdt_laddr: .dword */
  177. + 0x00000000,
  178. 0x00000000,
  179. /* fw_dyn: */
  180. };
  181. @@ -632,7 +639,7 @@ static void starfive_u_machine_init(MachineState *machine)
  182. /* Connect an SPI flash to SPI0 */
  183. flash_dev = qdev_new("is25wp256");
  184. - dinfo = drive_get_next(IF_MTD);
  185. + dinfo = drive_get(IF_MTD, 0, 0);
  186. if (dinfo) {
  187. qdev_prop_set_drive_err(flash_dev, "drive",
  188. blk_by_legacy_dinfo(dinfo),
  189. @@ -664,36 +671,20 @@ static void starfive_u_machine_set_start_in_flash(Object *obj, bool value, Error
  190. s->start_in_flash = value;
  191. }
  192. -static void starfive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
  193. - const char *name, void *opaque,
  194. - Error **errp)
  195. -{
  196. - visit_type_uint32(v, name, (uint32_t *)opaque, errp);
  197. -}
  198. -
  199. -static void starfive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
  200. - const char *name, void *opaque,
  201. - Error **errp)
  202. -{
  203. - visit_type_uint32(v, name, (uint32_t *)opaque, errp);
  204. -}
  205. -
  206. static void starfive_u_machine_instance_init(Object *obj)
  207. {
  208. StarFiveUState *s = RISCV_U_MACHINE(obj);
  209. s->start_in_flash = false;
  210. s->msel = 0;
  211. - object_property_add(obj, "msel", "uint32",
  212. - starfive_u_machine_get_uint32_prop,
  213. - starfive_u_machine_set_uint32_prop, NULL, &s->msel);
  214. + object_property_add_uint32_ptr(obj, "msel", &s->msel,
  215. + OBJ_PROP_FLAG_READWRITE);
  216. object_property_set_description(obj, "msel",
  217. "Mode Select (MSEL[3:0]) pin state");
  218. s->serial = OTP_SERIAL;
  219. - object_property_add(obj, "serial", "uint32",
  220. - starfive_u_machine_get_uint32_prop,
  221. - starfive_u_machine_set_uint32_prop, NULL, &s->serial);
  222. + object_property_add_uint32_ptr(obj, "serial", &s->serial,
  223. + OBJ_PROP_FLAG_READWRITE);
  224. object_property_set_description(obj, "serial", "Board serial number");
  225. }
  226. @@ -707,6 +698,7 @@ static void starfive_u_machine_class_init(ObjectClass *oc, void *data)
  227. mc->min_cpus = STARFIVE_U_MANAGEMENT_CPU_COUNT;
  228. mc->default_cpu_type = SIFIVE_U_CPU;
  229. mc->default_cpus = mc->min_cpus;
  230. + mc->default_ram_id = "riscv.sifive.u.ram";
  231. object_class_property_add_bool(oc, "start-in-flash",
  232. starfive_u_machine_get_start_in_flash,
  233. @@ -759,7 +751,6 @@ static void starfive_u_soc_realize(DeviceState *dev, Error **errp)
  234. MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
  235. MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
  236. char *plic_hart_config;
  237. - size_t plic_hart_config_len;
  238. int i;
  239. NICInfo *nd = &nd_table[0];
  240. @@ -768,7 +759,7 @@ static void starfive_u_soc_realize(DeviceState *dev, Error **errp)
  241. qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
  242. qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
  243. - sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
  244. + sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
  245. /*
  246. * The cluster must be realized after the RISC-V hart array container,
  247. * as the container's CPU object is only created on realize, and the
  248. @@ -798,22 +789,11 @@ static void starfive_u_soc_realize(DeviceState *dev, Error **errp)
  249. l2lim_mem);
  250. /* create PLIC hart topology configuration string */
  251. - plic_hart_config_len = (strlen(STARFIVE_U_PLIC_HART_CONFIG) + 1) *
  252. - ms->smp.cpus;
  253. - plic_hart_config = g_malloc0(plic_hart_config_len);
  254. - for (i = 0; i < ms->smp.cpus; i++) {
  255. - if (i != 0) {
  256. - strncat(plic_hart_config, "," STARFIVE_U_PLIC_HART_CONFIG,
  257. - plic_hart_config_len);
  258. - } else {
  259. - strncat(plic_hart_config, "M", plic_hart_config_len);
  260. - }
  261. - plic_hart_config_len -= (strlen(STARFIVE_U_PLIC_HART_CONFIG) + 1);
  262. - }
  263. + plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
  264. /* MMIO */
  265. s->plic = sifive_plic_create(memmap[STARFIVE_U_DEV_PLIC].base,
  266. - plic_hart_config, 0,
  267. + plic_hart_config, ms->smp.cpus, 0,
  268. STARFIVE_U_PLIC_NUM_SOURCES,
  269. STARFIVE_U_PLIC_NUM_PRIORITIES,
  270. STARFIVE_U_PLIC_PRIORITY_BASE,
  271. @@ -828,10 +808,13 @@ static void starfive_u_soc_realize(DeviceState *dev, Error **errp)
  272. serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), STARFIVE_U_UART0_IRQ));
  273. sifive_uart_create(system_memory, memmap[STARFIVE_U_DEV_UART1].base,
  274. serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), STARFIVE_U_UART1_IRQ));
  275. - sifive_clint_create(memmap[STARFIVE_U_DEV_CLINT].base,
  276. - memmap[STARFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
  277. - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
  278. - SIFIVE_CLINT_TIMEBASE_FREQ, false);
  279. + riscv_aclint_swi_create(memmap[STARFIVE_U_DEV_CLINT].base, 0,
  280. + ms->smp.cpus, false);
  281. + riscv_aclint_mtimer_create(memmap[STARFIVE_U_DEV_CLINT].base +
  282. + RISCV_ACLINT_SWI_SIZE,
  283. + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
  284. + RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
  285. + CLINT_TIMEBASE_FREQ, false);
  286. sifive_test_create(memmap[STARFIVE_U_DEV_TEST].base);
  287. if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
  288. --
  289. 2.25.1