0003-duhhe-bare-metal-sdk-support-based-on-sifive_u.patch 47 KB

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  1. From de231c5356b11a911bd02de36c0848f7765ddb37 Mon Sep 17 00:00:00 2001
  2. From: "demin.han" <demin.han@starfivetech.com>
  3. Date: Fri, 15 Apr 2022 15:50:43 +0800
  4. Subject: [PATCH 3/6] duhhe bare-metal-sdk support based on sifive_u
  5. 1. remove e cluster
  6. 2. add test dev
  7. 3. change UART0 memmap
  8. ---
  9. configs/devices/riscv64-softmmu/default.mak | 1 +
  10. hw/riscv/Kconfig | 16 +
  11. hw/riscv/meson.build | 1 +
  12. hw/riscv/starfive_u.c | 939 ++++++++++++++++++++
  13. include/hw/riscv/starfive_u.h | 156 ++++
  14. 5 files changed, 1113 insertions(+)
  15. create mode 100644 hw/riscv/starfive_u.c
  16. create mode 100644 include/hw/riscv/starfive_u.h
  17. diff --git a/configs/devices/riscv64-softmmu/default.mak b/configs/devices/riscv64-softmmu/default.mak
  18. index bc69301fa4..4c336b78c5 100644
  19. --- a/configs/devices/riscv64-softmmu/default.mak
  20. +++ b/configs/devices/riscv64-softmmu/default.mak
  21. @@ -14,3 +14,4 @@ CONFIG_SIFIVE_U=y
  22. CONFIG_RISCV_VIRT=y
  23. CONFIG_MICROCHIP_PFSOC=y
  24. CONFIG_SHAKTI_C=y
  25. +CONFIG_STARFIVE_U=y
  26. diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
  27. index 79ff61c464..369495f2fe 100644
  28. --- a/hw/riscv/Kconfig
  29. +++ b/hw/riscv/Kconfig
  30. @@ -85,3 +85,19 @@ config SPIKE
  31. select MSI_NONBROKEN
  32. select RISCV_ACLINT
  33. select SIFIVE_PLIC
  34. +
  35. +config STARFIVE_U
  36. + bool
  37. + select CADENCE
  38. + select MSI_NONBROKEN
  39. + select SIFIVE_CLINT
  40. + select SIFIVE_GPIO
  41. + select SIFIVE_PDMA
  42. + select SIFIVE_PLIC
  43. + select SIFIVE_SPI
  44. + select SIFIVE_UART
  45. + select SIFIVE_U_OTP
  46. + select SIFIVE_U_PRCI
  47. + select SSI_M25P80
  48. + select SSI_SD
  49. + select UNIMP
  50. \ No newline at end of file
  51. diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
  52. index ab6cae57ea..80e9f4d077 100644
  53. --- a/hw/riscv/meson.build
  54. +++ b/hw/riscv/meson.build
  55. @@ -9,5 +9,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  56. riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  57. riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
  58. riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
  59. +riscv_ss.add(when: 'CONFIG_STARFIVE_U', if_true: files('starfive_u.c'))
  60. hw_arch += {'riscv': riscv_ss}
  61. diff --git a/hw/riscv/starfive_u.c b/hw/riscv/starfive_u.c
  62. new file mode 100644
  63. index 0000000000..c8e27ab805
  64. --- /dev/null
  65. +++ b/hw/riscv/starfive_u.c
  66. @@ -0,0 +1,939 @@
  67. +/*
  68. + * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
  69. + *
  70. + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
  71. + * Copyright (c) 2017 SiFive, Inc.
  72. + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
  73. + *
  74. + * Provides a board compatible with the SiFive Freedom U SDK:
  75. + *
  76. + * 0) UART
  77. + * 1) CLINT (Core Level Interruptor)
  78. + * 2) PLIC (Platform Level Interrupt Controller)
  79. + * 3) PRCI (Power, Reset, Clock, Interrupt)
  80. + * 4) GPIO (General Purpose Input/Output Controller)
  81. + * 5) OTP (One-Time Programmable) memory with stored serial number
  82. + * 6) GEM (Gigabit Ethernet Controller) and management block
  83. + * 7) DMA (Direct Memory Access Controller)
  84. + * 8) SPI0 connected to an SPI flash
  85. + * 9) SPI2 connected to an SD card
  86. + *
  87. + * This board currently generates devicetree dynamically that indicates at least
  88. + * two harts and up to five harts.
  89. + *
  90. + * This program is free software; you can redistribute it and/or modify it
  91. + * under the terms and conditions of the GNU General Public License,
  92. + * version 2 or later, as published by the Free Software Foundation.
  93. + *
  94. + * This program is distributed in the hope it will be useful, but WITHOUT
  95. + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  96. + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  97. + * more details.
  98. + *
  99. + * You should have received a copy of the GNU General Public License along with
  100. + * this program. If not, see <http://www.gnu.org/licenses/>.
  101. + */
  102. +
  103. +#include "qemu/osdep.h"
  104. +#include "qemu/log.h"
  105. +#include "qemu/error-report.h"
  106. +#include "qapi/error.h"
  107. +#include "qapi/visitor.h"
  108. +#include "hw/boards.h"
  109. +#include "hw/irq.h"
  110. +#include "hw/loader.h"
  111. +#include "hw/sysbus.h"
  112. +#include "hw/char/serial.h"
  113. +#include "hw/cpu/cluster.h"
  114. +#include "hw/misc/unimp.h"
  115. +#include "hw/ssi/ssi.h"
  116. +#include "target/riscv/cpu.h"
  117. +#include "hw/riscv/riscv_hart.h"
  118. +#include "hw/riscv/starfive_u.h"
  119. +#include "hw/riscv/boot.h"
  120. +#include "hw/char/sifive_uart.h"
  121. +#include "hw/intc/sifive_clint.h"
  122. +#include "hw/intc/sifive_plic.h"
  123. +#include "hw/misc/sifive_test.h"
  124. +#include "chardev/char.h"
  125. +#include "net/eth.h"
  126. +#include "sysemu/arch_init.h"
  127. +#include "sysemu/device_tree.h"
  128. +#include "sysemu/runstate.h"
  129. +#include "sysemu/sysemu.h"
  130. +
  131. +#include <libfdt.h>
  132. +
  133. +static const MemMapEntry starfive_u_memmap[] = {
  134. + [STARFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
  135. + [STARFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
  136. + [STARFIVE_U_DEV_TEST] = { 0x100000, 0x1000 },
  137. + [STARFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
  138. + [STARFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
  139. + [STARFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 },
  140. + [STARFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
  141. + [STARFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
  142. + [STARFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
  143. + [STARFIVE_U_DEV_UART0] = { 0x10012000, 0x1000 },
  144. + [STARFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
  145. + [STARFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 },
  146. + [STARFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 },
  147. + [STARFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
  148. + [STARFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
  149. + [STARFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
  150. + [STARFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
  151. + [STARFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
  152. + [STARFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
  153. + [STARFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
  154. +};
  155. +
  156. +#define OTP_SERIAL 1
  157. +#define GEM_REVISION 0x10070109
  158. +
  159. +static void create_fdt(StarFiveUState *s, const MemMapEntry *memmap,
  160. + uint64_t mem_size, const char *cmdline, bool is_32_bit)
  161. +{
  162. + MachineState *ms = MACHINE(qdev_get_machine());
  163. + void *fdt;
  164. + int cpu;
  165. + uint32_t *cells;
  166. + char *nodename;
  167. + char ethclk_names[] = "pclk\0hclk";
  168. + uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
  169. + uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
  170. +
  171. + if (ms->dtb) {
  172. + fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size);
  173. + if (!fdt) {
  174. + error_report("load_device_tree() failed");
  175. + exit(1);
  176. + }
  177. + goto update_bootargs;
  178. + } else {
  179. + fdt = s->fdt = create_device_tree(&s->fdt_size);
  180. + if (!fdt) {
  181. + error_report("create_device_tree() failed");
  182. + exit(1);
  183. + }
  184. + }
  185. +
  186. + qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
  187. + qemu_fdt_setprop_string(fdt, "/", "compatible",
  188. + "sifive,hifive-unleashed-a00");
  189. + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
  190. + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
  191. +
  192. + qemu_fdt_add_subnode(fdt, "/soc");
  193. + qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
  194. + qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
  195. + qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
  196. + qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
  197. +
  198. + hfclk_phandle = phandle++;
  199. + nodename = g_strdup_printf("/hfclk");
  200. + qemu_fdt_add_subnode(fdt, nodename);
  201. + qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
  202. + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
  203. + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
  204. + STARFIVE_U_HFCLK_FREQ);
  205. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
  206. + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
  207. + g_free(nodename);
  208. +
  209. + rtcclk_phandle = phandle++;
  210. + nodename = g_strdup_printf("/rtcclk");
  211. + qemu_fdt_add_subnode(fdt, nodename);
  212. + qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
  213. + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
  214. + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
  215. + STARFIVE_U_RTCCLK_FREQ);
  216. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
  217. + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
  218. + g_free(nodename);
  219. +
  220. + nodename = g_strdup_printf("/memory@%lx",
  221. + (long)memmap[STARFIVE_U_DEV_DRAM].base);
  222. + qemu_fdt_add_subnode(fdt, nodename);
  223. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  224. + memmap[STARFIVE_U_DEV_DRAM].base >> 32, memmap[STARFIVE_U_DEV_DRAM].base,
  225. + mem_size >> 32, mem_size);
  226. + qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
  227. + g_free(nodename);
  228. +
  229. + qemu_fdt_add_subnode(fdt, "/cpus");
  230. + qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
  231. + SIFIVE_CLINT_TIMEBASE_FREQ);
  232. + qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
  233. + qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
  234. +
  235. + for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
  236. + int cpu_phandle = phandle++;
  237. + nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
  238. + char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
  239. + char *isa;
  240. + qemu_fdt_add_subnode(fdt, nodename);
  241. + /* cpu 0 is the management hart that does not have mmu */
  242. + if (cpu != 0) {
  243. + if (is_32_bit) {
  244. + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
  245. + } else {
  246. + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
  247. + }
  248. + isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
  249. + } else {
  250. + isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu]);
  251. + }
  252. + qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
  253. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
  254. + qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
  255. + qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
  256. + qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
  257. + qemu_fdt_add_subnode(fdt, intc);
  258. + qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
  259. + qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
  260. + qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
  261. + qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
  262. + g_free(isa);
  263. + g_free(intc);
  264. + g_free(nodename);
  265. + }
  266. +
  267. + cells = g_new0(uint32_t, ms->smp.cpus * 4);
  268. + for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
  269. + nodename =
  270. + g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
  271. + uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
  272. + cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
  273. + cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
  274. + cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
  275. + cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
  276. + g_free(nodename);
  277. + }
  278. + nodename = g_strdup_printf("/soc/clint@%lx",
  279. + (long)memmap[STARFIVE_U_DEV_CLINT].base);
  280. + qemu_fdt_add_subnode(fdt, nodename);
  281. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
  282. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  283. + 0x0, memmap[STARFIVE_U_DEV_CLINT].base,
  284. + 0x0, memmap[STARFIVE_U_DEV_CLINT].size);
  285. + qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
  286. + cells, ms->smp.cpus * sizeof(uint32_t) * 4);
  287. + g_free(cells);
  288. + g_free(nodename);
  289. +
  290. + nodename = g_strdup_printf("/soc/otp@%lx",
  291. + (long)memmap[STARFIVE_U_DEV_OTP].base);
  292. + qemu_fdt_add_subnode(fdt, nodename);
  293. + qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
  294. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  295. + 0x0, memmap[STARFIVE_U_DEV_OTP].base,
  296. + 0x0, memmap[STARFIVE_U_DEV_OTP].size);
  297. + qemu_fdt_setprop_string(fdt, nodename, "compatible",
  298. + "sifive,fu540-c000-otp");
  299. + g_free(nodename);
  300. +
  301. + prci_phandle = phandle++;
  302. + nodename = g_strdup_printf("/soc/clock-controller@%lx",
  303. + (long)memmap[STARFIVE_U_DEV_PRCI].base);
  304. + qemu_fdt_add_subnode(fdt, nodename);
  305. + qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
  306. + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
  307. + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
  308. + hfclk_phandle, rtcclk_phandle);
  309. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  310. + 0x0, memmap[STARFIVE_U_DEV_PRCI].base,
  311. + 0x0, memmap[STARFIVE_U_DEV_PRCI].size);
  312. + qemu_fdt_setprop_string(fdt, nodename, "compatible",
  313. + "sifive,fu540-c000-prci");
  314. + g_free(nodename);
  315. +
  316. + plic_phandle = phandle++;
  317. + cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
  318. + for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
  319. + nodename =
  320. + g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
  321. + uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
  322. + /* cpu 0 is the management hart that does not have S-mode */
  323. + if (cpu == 0) {
  324. + cells[0] = cpu_to_be32(intc_phandle);
  325. + cells[1] = cpu_to_be32(IRQ_M_EXT);
  326. + } else {
  327. + cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
  328. + cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
  329. + cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
  330. + cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
  331. + }
  332. + g_free(nodename);
  333. + }
  334. + nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
  335. + (long)memmap[STARFIVE_U_DEV_PLIC].base);
  336. + qemu_fdt_add_subnode(fdt, nodename);
  337. + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
  338. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
  339. + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
  340. + qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
  341. + cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
  342. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  343. + 0x0, memmap[STARFIVE_U_DEV_PLIC].base,
  344. + 0x0, memmap[STARFIVE_U_DEV_PLIC].size);
  345. + qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
  346. + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
  347. + plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
  348. + g_free(cells);
  349. + g_free(nodename);
  350. +
  351. + gpio_phandle = phandle++;
  352. + nodename = g_strdup_printf("/soc/gpio@%lx",
  353. + (long)memmap[STARFIVE_U_DEV_GPIO].base);
  354. + qemu_fdt_add_subnode(fdt, nodename);
  355. + qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
  356. + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
  357. + prci_phandle, PRCI_CLK_TLCLK);
  358. + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
  359. + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
  360. + qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
  361. + qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
  362. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  363. + 0x0, memmap[STARFIVE_U_DEV_GPIO].base,
  364. + 0x0, memmap[STARFIVE_U_DEV_GPIO].size);
  365. + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", STARFIVE_U_GPIO_IRQ0,
  366. + STARFIVE_U_GPIO_IRQ1, STARFIVE_U_GPIO_IRQ2, STARFIVE_U_GPIO_IRQ3,
  367. + STARFIVE_U_GPIO_IRQ4, STARFIVE_U_GPIO_IRQ5, STARFIVE_U_GPIO_IRQ6,
  368. + STARFIVE_U_GPIO_IRQ7, STARFIVE_U_GPIO_IRQ8, STARFIVE_U_GPIO_IRQ9,
  369. + STARFIVE_U_GPIO_IRQ10, STARFIVE_U_GPIO_IRQ11, STARFIVE_U_GPIO_IRQ12,
  370. + STARFIVE_U_GPIO_IRQ13, STARFIVE_U_GPIO_IRQ14, STARFIVE_U_GPIO_IRQ15);
  371. + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
  372. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
  373. + g_free(nodename);
  374. +
  375. + nodename = g_strdup_printf("/gpio-restart");
  376. + qemu_fdt_add_subnode(fdt, nodename);
  377. + qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
  378. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
  379. + g_free(nodename);
  380. +
  381. + nodename = g_strdup_printf("/soc/dma@%lx",
  382. + (long)memmap[STARFIVE_U_DEV_PDMA].base);
  383. + qemu_fdt_add_subnode(fdt, nodename);
  384. + qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
  385. + qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
  386. + STARFIVE_U_PDMA_IRQ0, STARFIVE_U_PDMA_IRQ1, STARFIVE_U_PDMA_IRQ2,
  387. + STARFIVE_U_PDMA_IRQ3, STARFIVE_U_PDMA_IRQ4, STARFIVE_U_PDMA_IRQ5,
  388. + STARFIVE_U_PDMA_IRQ6, STARFIVE_U_PDMA_IRQ7);
  389. + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
  390. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  391. + 0x0, memmap[STARFIVE_U_DEV_PDMA].base,
  392. + 0x0, memmap[STARFIVE_U_DEV_PDMA].size);
  393. + qemu_fdt_setprop_string(fdt, nodename, "compatible",
  394. + "sifive,fu540-c000-pdma");
  395. + g_free(nodename);
  396. +
  397. + nodename = g_strdup_printf("/soc/cache-controller@%lx",
  398. + (long)memmap[STARFIVE_U_DEV_L2CC].base);
  399. + qemu_fdt_add_subnode(fdt, nodename);
  400. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  401. + 0x0, memmap[STARFIVE_U_DEV_L2CC].base,
  402. + 0x0, memmap[STARFIVE_U_DEV_L2CC].size);
  403. + qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
  404. + STARFIVE_U_L2CC_IRQ0, STARFIVE_U_L2CC_IRQ1, STARFIVE_U_L2CC_IRQ2);
  405. + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
  406. + qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
  407. + qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
  408. + qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
  409. + qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
  410. + qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
  411. + qemu_fdt_setprop_string(fdt, nodename, "compatible",
  412. + "sifive,fu540-c000-ccache");
  413. + g_free(nodename);
  414. +
  415. + nodename = g_strdup_printf("/soc/spi@%lx",
  416. + (long)memmap[STARFIVE_U_DEV_QSPI2].base);
  417. + qemu_fdt_add_subnode(fdt, nodename);
  418. + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
  419. + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
  420. + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
  421. + prci_phandle, PRCI_CLK_TLCLK);
  422. + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", STARFIVE_U_QSPI2_IRQ);
  423. + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
  424. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  425. + 0x0, memmap[STARFIVE_U_DEV_QSPI2].base,
  426. + 0x0, memmap[STARFIVE_U_DEV_QSPI2].size);
  427. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
  428. + g_free(nodename);
  429. +
  430. + nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
  431. + (long)memmap[STARFIVE_U_DEV_QSPI2].base);
  432. + qemu_fdt_add_subnode(fdt, nodename);
  433. + qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
  434. + qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
  435. + qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
  436. + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
  437. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
  438. + g_free(nodename);
  439. +
  440. + nodename = g_strdup_printf("/soc/spi@%lx",
  441. + (long)memmap[STARFIVE_U_DEV_QSPI0].base);
  442. + qemu_fdt_add_subnode(fdt, nodename);
  443. + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
  444. + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
  445. + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
  446. + prci_phandle, PRCI_CLK_TLCLK);
  447. + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", STARFIVE_U_QSPI0_IRQ);
  448. + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
  449. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  450. + 0x0, memmap[STARFIVE_U_DEV_QSPI0].base,
  451. + 0x0, memmap[STARFIVE_U_DEV_QSPI0].size);
  452. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
  453. + g_free(nodename);
  454. +
  455. + nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
  456. + (long)memmap[STARFIVE_U_DEV_QSPI0].base);
  457. + qemu_fdt_add_subnode(fdt, nodename);
  458. + qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
  459. + qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
  460. + qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
  461. + qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
  462. + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
  463. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
  464. + g_free(nodename);
  465. +
  466. + phy_phandle = phandle++;
  467. + nodename = g_strdup_printf("/soc/ethernet@%lx",
  468. + (long)memmap[STARFIVE_U_DEV_GEM].base);
  469. + qemu_fdt_add_subnode(fdt, nodename);
  470. + qemu_fdt_setprop_string(fdt, nodename, "compatible",
  471. + "sifive,fu540-c000-gem");
  472. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  473. + 0x0, memmap[STARFIVE_U_DEV_GEM].base,
  474. + 0x0, memmap[STARFIVE_U_DEV_GEM].size,
  475. + 0x0, memmap[STARFIVE_U_DEV_GEM_MGMT].base,
  476. + 0x0, memmap[STARFIVE_U_DEV_GEM_MGMT].size);
  477. + qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
  478. + qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
  479. + qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
  480. + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
  481. + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", STARFIVE_U_GEM_IRQ);
  482. + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
  483. + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
  484. + qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
  485. + sizeof(ethclk_names));
  486. + qemu_fdt_setprop(fdt, nodename, "local-mac-address",
  487. + s->soc.gem.conf.macaddr.a, ETH_ALEN);
  488. + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
  489. + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
  490. +
  491. + qemu_fdt_add_subnode(fdt, "/aliases");
  492. + qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
  493. +
  494. + g_free(nodename);
  495. +
  496. + nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
  497. + (long)memmap[STARFIVE_U_DEV_GEM].base);
  498. + qemu_fdt_add_subnode(fdt, nodename);
  499. + qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
  500. + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
  501. + g_free(nodename);
  502. +
  503. + nodename = g_strdup_printf("/soc/serial@%lx",
  504. + (long)memmap[STARFIVE_U_DEV_UART1].base);
  505. + qemu_fdt_add_subnode(fdt, nodename);
  506. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
  507. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  508. + 0x0, memmap[STARFIVE_U_DEV_UART1].base,
  509. + 0x0, memmap[STARFIVE_U_DEV_UART1].size);
  510. + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
  511. + prci_phandle, PRCI_CLK_TLCLK);
  512. + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
  513. + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", STARFIVE_U_UART1_IRQ);
  514. +
  515. + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
  516. + g_free(nodename);
  517. +
  518. + nodename = g_strdup_printf("/soc/serial@%lx",
  519. + (long)memmap[STARFIVE_U_DEV_UART0].base);
  520. + qemu_fdt_add_subnode(fdt, nodename);
  521. + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
  522. + qemu_fdt_setprop_cells(fdt, nodename, "reg",
  523. + 0x0, memmap[STARFIVE_U_DEV_UART0].base,
  524. + 0x0, memmap[STARFIVE_U_DEV_UART0].size);
  525. + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
  526. + prci_phandle, PRCI_CLK_TLCLK);
  527. + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
  528. + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", STARFIVE_U_UART0_IRQ);
  529. +
  530. + qemu_fdt_add_subnode(fdt, "/chosen");
  531. + qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
  532. + qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
  533. +
  534. + g_free(nodename);
  535. +
  536. +update_bootargs:
  537. + if (cmdline) {
  538. + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
  539. + }
  540. +}
  541. +
  542. +static void starfive_u_machine_reset(void *opaque, int n, int level)
  543. +{
  544. + /* gpio pin active low triggers reset */
  545. + if (!level) {
  546. + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
  547. + }
  548. +}
  549. +
  550. +static void starfive_u_machine_init(MachineState *machine)
  551. +{
  552. + const MemMapEntry *memmap = starfive_u_memmap;
  553. + StarFiveUState *s = RISCV_U_MACHINE(machine);
  554. + MemoryRegion *system_memory = get_system_memory();
  555. + MemoryRegion *main_mem = g_new(MemoryRegion, 1);
  556. + MemoryRegion *flash0 = g_new(MemoryRegion, 1);
  557. + target_ulong start_addr = memmap[STARFIVE_U_DEV_DRAM].base;
  558. + target_ulong firmware_end_addr, kernel_start_addr;
  559. + uint32_t start_addr_hi32 = 0x00000000;
  560. + int i;
  561. + uint32_t fdt_load_addr;
  562. + uint64_t kernel_entry;
  563. + DriveInfo *dinfo;
  564. + DeviceState *flash_dev, *sd_dev;
  565. + qemu_irq flash_cs, sd_cs;
  566. +
  567. + /* Initialize SoC */
  568. + object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
  569. + object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
  570. + &error_abort);
  571. + object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
  572. + &error_abort);
  573. + qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
  574. +
  575. + /* register RAM */
  576. + memory_region_init_ram(main_mem, NULL, "riscv.starfive.u.ram",
  577. + machine->ram_size, &error_fatal);
  578. + memory_region_add_subregion(system_memory, memmap[STARFIVE_U_DEV_DRAM].base,
  579. + main_mem);
  580. +
  581. + /* register QSPI0 Flash */
  582. + memory_region_init_ram(flash0, NULL, "riscv.starfive.u.flash0",
  583. + memmap[STARFIVE_U_DEV_FLASH0].size, &error_fatal);
  584. + memory_region_add_subregion(system_memory, memmap[STARFIVE_U_DEV_FLASH0].base,
  585. + flash0);
  586. +
  587. + /* register gpio-restart */
  588. + qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
  589. + qemu_allocate_irq(starfive_u_machine_reset, NULL, 0));
  590. +
  591. + /* create device tree */
  592. + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
  593. + riscv_is_32bit(&s->soc.u_cpus));
  594. +
  595. + if (s->start_in_flash) {
  596. + /*
  597. + * If start_in_flash property is given, assign s->msel to a value
  598. + * that representing booting from QSPI0 memory-mapped flash.
  599. + *
  600. + * This also means that when both start_in_flash and msel properties
  601. + * are given, start_in_flash takes the precedence over msel.
  602. + *
  603. + * Note this is to keep backward compatibility not to break existing
  604. + * users that use start_in_flash property.
  605. + */
  606. + s->msel = MSEL_MEMMAP_QSPI0_FLASH;
  607. + }
  608. +
  609. + switch (s->msel) {
  610. + case MSEL_MEMMAP_QSPI0_FLASH:
  611. + start_addr = memmap[STARFIVE_U_DEV_FLASH0].base;
  612. + break;
  613. + case MSEL_L2LIM_QSPI0_FLASH:
  614. + case MSEL_L2LIM_QSPI2_SD:
  615. + start_addr = memmap[STARFIVE_U_DEV_L2LIM].base;
  616. + break;
  617. + default:
  618. + start_addr = memmap[STARFIVE_U_DEV_DRAM].base;
  619. + break;
  620. + }
  621. +
  622. + if (riscv_is_32bit(&s->soc.u_cpus)) {
  623. + firmware_end_addr = riscv_find_and_load_firmware(machine,
  624. + "opensbi-riscv32-generic-fw_dynamic.bin",
  625. + start_addr, NULL);
  626. + } else {
  627. + firmware_end_addr = riscv_find_and_load_firmware(machine,
  628. + "opensbi-riscv64-generic-fw_dynamic.bin",
  629. + start_addr, NULL);
  630. + }
  631. +
  632. + if (machine->kernel_filename) {
  633. + kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
  634. + firmware_end_addr);
  635. +
  636. + kernel_entry = riscv_load_kernel(machine->kernel_filename,
  637. + kernel_start_addr, NULL);
  638. +
  639. + if (machine->initrd_filename) {
  640. + hwaddr start;
  641. + hwaddr end = riscv_load_initrd(machine->initrd_filename,
  642. + machine->ram_size, kernel_entry,
  643. + &start);
  644. + qemu_fdt_setprop_cell(s->fdt, "/chosen",
  645. + "linux,initrd-start", start);
  646. + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
  647. + end);
  648. + }
  649. + } else {
  650. + /*
  651. + * If dynamic firmware is used, it doesn't know where is the next mode
  652. + * if kernel argument is not set.
  653. + */
  654. + kernel_entry = 0;
  655. + }
  656. +
  657. + /* Compute the fdt load address in dram */
  658. + fdt_load_addr = riscv_load_fdt(memmap[STARFIVE_U_DEV_DRAM].base,
  659. + machine->ram_size, s->fdt);
  660. + if (!riscv_is_32bit(&s->soc.u_cpus)) {
  661. + start_addr_hi32 = (uint64_t)start_addr >> 32;
  662. + }
  663. +
  664. + /* reset vector */
  665. + uint32_t reset_vec[11] = {
  666. + s->msel, /* MSEL pin state */
  667. + 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
  668. + 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
  669. + 0xf1402573, /* csrr a0, mhartid */
  670. + 0,
  671. + 0,
  672. + 0x00028067, /* jr t0 */
  673. + start_addr, /* start: .dword */
  674. + start_addr_hi32,
  675. + fdt_load_addr, /* fdt_laddr: .dword */
  676. + 0x00000000,
  677. + /* fw_dyn: */
  678. + };
  679. + if (riscv_is_32bit(&s->soc.u_cpus)) {
  680. + reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */
  681. + reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */
  682. + } else {
  683. + reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */
  684. + reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */
  685. + }
  686. +
  687. +
  688. + /* copy in the reset vector in little_endian byte order */
  689. + for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
  690. + reset_vec[i] = cpu_to_le32(reset_vec[i]);
  691. + }
  692. + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
  693. + memmap[STARFIVE_U_DEV_MROM].base, &address_space_memory);
  694. +
  695. + riscv_rom_copy_firmware_info(machine, memmap[STARFIVE_U_DEV_MROM].base,
  696. + memmap[STARFIVE_U_DEV_MROM].size,
  697. + sizeof(reset_vec), kernel_entry);
  698. +
  699. + /* Connect an SPI flash to SPI0 */
  700. + flash_dev = qdev_new("is25wp256");
  701. + dinfo = drive_get_next(IF_MTD);
  702. + if (dinfo) {
  703. + qdev_prop_set_drive_err(flash_dev, "drive",
  704. + blk_by_legacy_dinfo(dinfo),
  705. + &error_fatal);
  706. + }
  707. + qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
  708. +
  709. + flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
  710. + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
  711. +
  712. + /* Connect an SD card to SPI2 */
  713. + sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
  714. +
  715. + sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
  716. + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
  717. +}
  718. +
  719. +static bool starfive_u_machine_get_start_in_flash(Object *obj, Error **errp)
  720. +{
  721. + StarFiveUState *s = RISCV_U_MACHINE(obj);
  722. +
  723. + return s->start_in_flash;
  724. +}
  725. +
  726. +static void starfive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
  727. +{
  728. + StarFiveUState *s = RISCV_U_MACHINE(obj);
  729. +
  730. + s->start_in_flash = value;
  731. +}
  732. +
  733. +static void starfive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
  734. + const char *name, void *opaque,
  735. + Error **errp)
  736. +{
  737. + visit_type_uint32(v, name, (uint32_t *)opaque, errp);
  738. +}
  739. +
  740. +static void starfive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
  741. + const char *name, void *opaque,
  742. + Error **errp)
  743. +{
  744. + visit_type_uint32(v, name, (uint32_t *)opaque, errp);
  745. +}
  746. +
  747. +static void starfive_u_machine_instance_init(Object *obj)
  748. +{
  749. + StarFiveUState *s = RISCV_U_MACHINE(obj);
  750. +
  751. + s->start_in_flash = false;
  752. + s->msel = 0;
  753. + object_property_add(obj, "msel", "uint32",
  754. + starfive_u_machine_get_uint32_prop,
  755. + starfive_u_machine_set_uint32_prop, NULL, &s->msel);
  756. + object_property_set_description(obj, "msel",
  757. + "Mode Select (MSEL[3:0]) pin state");
  758. +
  759. + s->serial = OTP_SERIAL;
  760. + object_property_add(obj, "serial", "uint32",
  761. + starfive_u_machine_get_uint32_prop,
  762. + starfive_u_machine_set_uint32_prop, NULL, &s->serial);
  763. + object_property_set_description(obj, "serial", "Board serial number");
  764. +}
  765. +
  766. +static void starfive_u_machine_class_init(ObjectClass *oc, void *data)
  767. +{
  768. + MachineClass *mc = MACHINE_CLASS(oc);
  769. +
  770. + mc->desc = "RISC-V Board compatible with SiFive U SDK";
  771. + mc->init = starfive_u_machine_init;
  772. + mc->max_cpus = STARFIVE_U_MANAGEMENT_CPU_COUNT + STARFIVE_U_COMPUTE_CPU_COUNT;
  773. + mc->min_cpus = STARFIVE_U_MANAGEMENT_CPU_COUNT;
  774. + mc->default_cpu_type = SIFIVE_U_CPU;
  775. + mc->default_cpus = mc->min_cpus;
  776. +
  777. + object_class_property_add_bool(oc, "start-in-flash",
  778. + starfive_u_machine_get_start_in_flash,
  779. + starfive_u_machine_set_start_in_flash);
  780. + object_class_property_set_description(oc, "start-in-flash",
  781. + "Set on to tell QEMU's ROM to jump to "
  782. + "flash. Otherwise QEMU will jump to DRAM "
  783. + "or L2LIM depending on the msel value");
  784. +}
  785. +
  786. +static const TypeInfo starfive_u_machine_typeinfo = {
  787. + .name = MACHINE_TYPE_NAME("starfive_u"),
  788. + .parent = TYPE_MACHINE,
  789. + .class_init = starfive_u_machine_class_init,
  790. + .instance_init = starfive_u_machine_instance_init,
  791. + .instance_size = sizeof(StarFiveUState),
  792. +};
  793. +
  794. +static void starfive_u_machine_init_register_types(void)
  795. +{
  796. + type_register_static(&starfive_u_machine_typeinfo);
  797. +}
  798. +
  799. +type_init(starfive_u_machine_init_register_types)
  800. +
  801. +static void starfive_u_soc_instance_init(Object *obj)
  802. +{
  803. + StarFiveUSoCState *s = RISCV_U_SOC(obj);
  804. + object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
  805. + qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 0);
  806. +
  807. + object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
  808. + TYPE_RISCV_HART_ARRAY);
  809. +
  810. + object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
  811. + object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
  812. + object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
  813. + object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
  814. + object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
  815. + object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
  816. + object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
  817. +}
  818. +
  819. +static void starfive_u_soc_realize(DeviceState *dev, Error **errp)
  820. +{
  821. + MachineState *ms = MACHINE(qdev_get_machine());
  822. + StarFiveUSoCState *s = RISCV_U_SOC(dev);
  823. + const MemMapEntry *memmap = starfive_u_memmap;
  824. + MemoryRegion *system_memory = get_system_memory();
  825. + MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
  826. + MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
  827. + char *plic_hart_config;
  828. + size_t plic_hart_config_len;
  829. + int i;
  830. + NICInfo *nd = &nd_table[0];
  831. +
  832. + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus);
  833. + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 0);
  834. + qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
  835. + qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
  836. +
  837. + sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
  838. + /*
  839. + * The cluster must be realized after the RISC-V hart array container,
  840. + * as the container's CPU object is only created on realize, and the
  841. + * CPU must exist and have been parented into the cluster before the
  842. + * cluster is realized.
  843. + */
  844. + qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
  845. +
  846. + /* boot rom */
  847. + memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.starfive.u.mrom",
  848. + memmap[STARFIVE_U_DEV_MROM].size, &error_fatal);
  849. + memory_region_add_subregion(system_memory, memmap[STARFIVE_U_DEV_MROM].base,
  850. + mask_rom);
  851. +
  852. + /*
  853. + * Add L2-LIM at reset size.
  854. + * This should be reduced in size as the L2 Cache Controller WayEnable
  855. + * register is incremented. Unfortunately I don't see a nice (or any) way
  856. + * to handle reducing or blocking out the L2 LIM while still allowing it
  857. + * be re returned to all enabled after a reset. For the time being, just
  858. + * leave it enabled all the time. This won't break anything, but will be
  859. + * too generous to misbehaving guests.
  860. + */
  861. + memory_region_init_ram(l2lim_mem, NULL, "riscv.starfive.u.l2lim",
  862. + memmap[STARFIVE_U_DEV_L2LIM].size, &error_fatal);
  863. + memory_region_add_subregion(system_memory, memmap[STARFIVE_U_DEV_L2LIM].base,
  864. + l2lim_mem);
  865. +
  866. + /* create PLIC hart topology configuration string */
  867. + plic_hart_config_len = (strlen(STARFIVE_U_PLIC_HART_CONFIG) + 1) *
  868. + ms->smp.cpus;
  869. + plic_hart_config = g_malloc0(plic_hart_config_len);
  870. + for (i = 0; i < ms->smp.cpus; i++) {
  871. + if (i != 0) {
  872. + strncat(plic_hart_config, "," STARFIVE_U_PLIC_HART_CONFIG,
  873. + plic_hart_config_len);
  874. + } else {
  875. + strncat(plic_hart_config, "M", plic_hart_config_len);
  876. + }
  877. + plic_hart_config_len -= (strlen(STARFIVE_U_PLIC_HART_CONFIG) + 1);
  878. + }
  879. +
  880. + /* MMIO */
  881. + s->plic = sifive_plic_create(memmap[STARFIVE_U_DEV_PLIC].base,
  882. + plic_hart_config, 0,
  883. + STARFIVE_U_PLIC_NUM_SOURCES,
  884. + STARFIVE_U_PLIC_NUM_PRIORITIES,
  885. + STARFIVE_U_PLIC_PRIORITY_BASE,
  886. + STARFIVE_U_PLIC_PENDING_BASE,
  887. + STARFIVE_U_PLIC_ENABLE_BASE,
  888. + STARFIVE_U_PLIC_ENABLE_STRIDE,
  889. + STARFIVE_U_PLIC_CONTEXT_BASE,
  890. + STARFIVE_U_PLIC_CONTEXT_STRIDE,
  891. + memmap[STARFIVE_U_DEV_PLIC].size);
  892. + g_free(plic_hart_config);
  893. + sifive_uart_create(system_memory, memmap[STARFIVE_U_DEV_UART0].base,
  894. + serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), STARFIVE_U_UART0_IRQ));
  895. + sifive_uart_create(system_memory, memmap[STARFIVE_U_DEV_UART1].base,
  896. + serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), STARFIVE_U_UART1_IRQ));
  897. + sifive_clint_create(memmap[STARFIVE_U_DEV_CLINT].base,
  898. + memmap[STARFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus,
  899. + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
  900. + SIFIVE_CLINT_TIMEBASE_FREQ, false);
  901. + sifive_test_create(memmap[STARFIVE_U_DEV_TEST].base);
  902. +
  903. + if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
  904. + return;
  905. + }
  906. + sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[STARFIVE_U_DEV_PRCI].base);
  907. +
  908. + qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
  909. + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
  910. + return;
  911. + }
  912. + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[STARFIVE_U_DEV_GPIO].base);
  913. +
  914. + /* Pass all GPIOs to the SOC layer so they are available to the board */
  915. + qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
  916. +
  917. + /* Connect GPIO interrupts to the PLIC */
  918. + for (i = 0; i < 16; i++) {
  919. + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
  920. + qdev_get_gpio_in(DEVICE(s->plic),
  921. + STARFIVE_U_GPIO_IRQ0 + i));
  922. + }
  923. +
  924. + /* PDMA */
  925. + sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
  926. + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[STARFIVE_U_DEV_PDMA].base);
  927. +
  928. + /* Connect PDMA interrupts to the PLIC */
  929. + for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
  930. + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
  931. + qdev_get_gpio_in(DEVICE(s->plic),
  932. + STARFIVE_U_PDMA_IRQ0 + i));
  933. + }
  934. +
  935. + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
  936. + if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
  937. + return;
  938. + }
  939. + sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[STARFIVE_U_DEV_OTP].base);
  940. +
  941. + /* FIXME use qdev NIC properties instead of nd_table[] */
  942. + if (nd->used) {
  943. + qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
  944. + qdev_set_nic_properties(DEVICE(&s->gem), nd);
  945. + }
  946. + object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
  947. + &error_abort);
  948. + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
  949. + return;
  950. + }
  951. + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[STARFIVE_U_DEV_GEM].base);
  952. + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
  953. + qdev_get_gpio_in(DEVICE(s->plic), STARFIVE_U_GEM_IRQ));
  954. +
  955. + create_unimplemented_device("riscv.starfive.u.gem-mgmt",
  956. + memmap[STARFIVE_U_DEV_GEM_MGMT].base, memmap[STARFIVE_U_DEV_GEM_MGMT].size);
  957. +
  958. + create_unimplemented_device("riscv.starfive.u.dmc",
  959. + memmap[STARFIVE_U_DEV_DMC].base, memmap[STARFIVE_U_DEV_DMC].size);
  960. +
  961. + create_unimplemented_device("riscv.starfive.u.l2cc",
  962. + memmap[STARFIVE_U_DEV_L2CC].base, memmap[STARFIVE_U_DEV_L2CC].size);
  963. +
  964. + sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
  965. + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
  966. + memmap[STARFIVE_U_DEV_QSPI0].base);
  967. + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
  968. + qdev_get_gpio_in(DEVICE(s->plic), STARFIVE_U_QSPI0_IRQ));
  969. + sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
  970. + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
  971. + memmap[STARFIVE_U_DEV_QSPI2].base);
  972. + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
  973. + qdev_get_gpio_in(DEVICE(s->plic), STARFIVE_U_QSPI2_IRQ));
  974. +}
  975. +
  976. +static Property starfive_u_soc_props[] = {
  977. + DEFINE_PROP_UINT32("serial", StarFiveUSoCState, serial, OTP_SERIAL),
  978. + DEFINE_PROP_STRING("cpu-type", StarFiveUSoCState, cpu_type),
  979. + DEFINE_PROP_END_OF_LIST()
  980. +};
  981. +
  982. +static void starfive_u_soc_class_init(ObjectClass *oc, void *data)
  983. +{
  984. + DeviceClass *dc = DEVICE_CLASS(oc);
  985. +
  986. + device_class_set_props(dc, starfive_u_soc_props);
  987. + dc->realize = starfive_u_soc_realize;
  988. + /* Reason: Uses serial_hds in realize function, thus can't be used twice */
  989. + dc->user_creatable = false;
  990. +}
  991. +
  992. +static const TypeInfo starfive_u_soc_type_info = {
  993. + .name = TYPE_RISCV_U_SOC,
  994. + .parent = TYPE_DEVICE,
  995. + .instance_size = sizeof(StarFiveUSoCState),
  996. + .instance_init = starfive_u_soc_instance_init,
  997. + .class_init = starfive_u_soc_class_init,
  998. +};
  999. +
  1000. +static void starfive_u_soc_register_types(void)
  1001. +{
  1002. + type_register_static(&starfive_u_soc_type_info);
  1003. +}
  1004. +
  1005. +type_init(starfive_u_soc_register_types)
  1006. diff --git a/include/hw/riscv/starfive_u.h b/include/hw/riscv/starfive_u.h
  1007. new file mode 100644
  1008. index 0000000000..3007480aa7
  1009. --- /dev/null
  1010. +++ b/include/hw/riscv/starfive_u.h
  1011. @@ -0,0 +1,156 @@
  1012. +/*
  1013. + * SiFive U series machine interface
  1014. + *
  1015. + * Copyright (c) 2017 SiFive, Inc.
  1016. + *
  1017. + * This program is free software; you can redistribute it and/or modify it
  1018. + * under the terms and conditions of the GNU General Public License,
  1019. + * version 2 or later, as published by the Free Software Foundation.
  1020. + *
  1021. + * This program is distributed in the hope it will be useful, but WITHOUT
  1022. + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  1023. + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  1024. + * more details.
  1025. + *
  1026. + * You should have received a copy of the GNU General Public License along with
  1027. + * this program. If not, see <http://www.gnu.org/licenses/>.
  1028. + */
  1029. +
  1030. +#ifndef HW_STARFIVE_U_H
  1031. +#define HW_STARFIVE_U_H
  1032. +
  1033. +#include "hw/dma/sifive_pdma.h"
  1034. +#include "hw/net/cadence_gem.h"
  1035. +#include "hw/riscv/riscv_hart.h"
  1036. +#include "hw/riscv/sifive_cpu.h"
  1037. +#include "hw/gpio/sifive_gpio.h"
  1038. +#include "hw/misc/sifive_u_otp.h"
  1039. +#include "hw/misc/sifive_u_prci.h"
  1040. +#include "hw/ssi/sifive_spi.h"
  1041. +
  1042. +#define TYPE_RISCV_U_SOC "riscv.starfive.u.soc"
  1043. +#define RISCV_U_SOC(obj) \
  1044. + OBJECT_CHECK(StarFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
  1045. +
  1046. +typedef struct StarFiveUSoCState {
  1047. + /*< private >*/
  1048. + DeviceState parent_obj;
  1049. +
  1050. + /*< public >*/
  1051. + CPUClusterState u_cluster;
  1052. + RISCVHartArrayState u_cpus;
  1053. + DeviceState *plic;
  1054. + SiFiveUPRCIState prci;
  1055. + SIFIVEGPIOState gpio;
  1056. + SiFiveUOTPState otp;
  1057. + SiFivePDMAState dma;
  1058. + SiFiveSPIState spi0;
  1059. + SiFiveSPIState spi2;
  1060. + CadenceGEMState gem;
  1061. +
  1062. + uint32_t serial;
  1063. + char *cpu_type;
  1064. +} StarFiveUSoCState;
  1065. +
  1066. +#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("starfive_u")
  1067. +#define RISCV_U_MACHINE(obj) \
  1068. + OBJECT_CHECK(StarFiveUState, (obj), TYPE_RISCV_U_MACHINE)
  1069. +
  1070. +typedef struct StarFiveUState {
  1071. + /*< private >*/
  1072. + MachineState parent_obj;
  1073. +
  1074. + /*< public >*/
  1075. + StarFiveUSoCState soc;
  1076. +
  1077. + void *fdt;
  1078. + int fdt_size;
  1079. +
  1080. + bool start_in_flash;
  1081. + uint32_t msel;
  1082. + uint32_t serial;
  1083. +} StarFiveUState;
  1084. +
  1085. +enum {
  1086. + STARFIVE_U_DEV_DEBUG,
  1087. + STARFIVE_U_DEV_MROM,
  1088. + STARFIVE_U_DEV_TEST,
  1089. + STARFIVE_U_DEV_CLINT,
  1090. + STARFIVE_U_DEV_L2CC,
  1091. + STARFIVE_U_DEV_PDMA,
  1092. + STARFIVE_U_DEV_L2LIM,
  1093. + STARFIVE_U_DEV_PLIC,
  1094. + STARFIVE_U_DEV_PRCI,
  1095. + STARFIVE_U_DEV_UART0,
  1096. + STARFIVE_U_DEV_UART1,
  1097. + STARFIVE_U_DEV_GPIO,
  1098. + STARFIVE_U_DEV_QSPI0,
  1099. + STARFIVE_U_DEV_QSPI2,
  1100. + STARFIVE_U_DEV_OTP,
  1101. + STARFIVE_U_DEV_DMC,
  1102. + STARFIVE_U_DEV_FLASH0,
  1103. + STARFIVE_U_DEV_DRAM,
  1104. + STARFIVE_U_DEV_GEM,
  1105. + STARFIVE_U_DEV_GEM_MGMT
  1106. +};
  1107. +
  1108. +enum {
  1109. + STARFIVE_U_L2CC_IRQ0 = 1,
  1110. + STARFIVE_U_L2CC_IRQ1 = 2,
  1111. + STARFIVE_U_L2CC_IRQ2 = 3,
  1112. + STARFIVE_U_UART0_IRQ = 4,
  1113. + STARFIVE_U_UART1_IRQ = 5,
  1114. + STARFIVE_U_QSPI2_IRQ = 6,
  1115. + STARFIVE_U_GPIO_IRQ0 = 7,
  1116. + STARFIVE_U_GPIO_IRQ1 = 8,
  1117. + STARFIVE_U_GPIO_IRQ2 = 9,
  1118. + STARFIVE_U_GPIO_IRQ3 = 10,
  1119. + STARFIVE_U_GPIO_IRQ4 = 11,
  1120. + STARFIVE_U_GPIO_IRQ5 = 12,
  1121. + STARFIVE_U_GPIO_IRQ6 = 13,
  1122. + STARFIVE_U_GPIO_IRQ7 = 14,
  1123. + STARFIVE_U_GPIO_IRQ8 = 15,
  1124. + STARFIVE_U_GPIO_IRQ9 = 16,
  1125. + STARFIVE_U_GPIO_IRQ10 = 17,
  1126. + STARFIVE_U_GPIO_IRQ11 = 18,
  1127. + STARFIVE_U_GPIO_IRQ12 = 19,
  1128. + STARFIVE_U_GPIO_IRQ13 = 20,
  1129. + STARFIVE_U_GPIO_IRQ14 = 21,
  1130. + STARFIVE_U_GPIO_IRQ15 = 22,
  1131. + STARFIVE_U_PDMA_IRQ0 = 23,
  1132. + STARFIVE_U_PDMA_IRQ1 = 24,
  1133. + STARFIVE_U_PDMA_IRQ2 = 25,
  1134. + STARFIVE_U_PDMA_IRQ3 = 26,
  1135. + STARFIVE_U_PDMA_IRQ4 = 27,
  1136. + STARFIVE_U_PDMA_IRQ5 = 28,
  1137. + STARFIVE_U_PDMA_IRQ6 = 29,
  1138. + STARFIVE_U_PDMA_IRQ7 = 30,
  1139. + STARFIVE_U_QSPI0_IRQ = 51,
  1140. + STARFIVE_U_GEM_IRQ = 53
  1141. +};
  1142. +
  1143. +enum {
  1144. + STARFIVE_U_HFCLK_FREQ = 33333333,
  1145. + STARFIVE_U_RTCCLK_FREQ = 1000000
  1146. +};
  1147. +
  1148. +enum {
  1149. + MSEL_MEMMAP_QSPI0_FLASH = 1,
  1150. + MSEL_L2LIM_QSPI0_FLASH = 6,
  1151. + MSEL_L2LIM_QSPI2_SD = 11
  1152. +};
  1153. +
  1154. +#define STARFIVE_U_MANAGEMENT_CPU_COUNT 1
  1155. +#define STARFIVE_U_COMPUTE_CPU_COUNT 4
  1156. +
  1157. +#define STARFIVE_U_PLIC_HART_CONFIG "MS"
  1158. +#define STARFIVE_U_PLIC_NUM_SOURCES 54
  1159. +#define STARFIVE_U_PLIC_NUM_PRIORITIES 7
  1160. +#define STARFIVE_U_PLIC_PRIORITY_BASE 0x04
  1161. +#define STARFIVE_U_PLIC_PENDING_BASE 0x1000
  1162. +#define STARFIVE_U_PLIC_ENABLE_BASE 0x2000
  1163. +#define STARFIVE_U_PLIC_ENABLE_STRIDE 0x80
  1164. +#define STARFIVE_U_PLIC_CONTEXT_BASE 0x200000
  1165. +#define STARFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
  1166. +
  1167. +#endif
  1168. --
  1169. 2.25.1