0002-Fix-cache-instruction-bug.patch 1.7 KB

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  1. From d55020858c4dfa834deb17f3682e3adae9287ac3 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Tue, 22 Mar 2022 02:26:39 -0700
  4. Subject: [PATCH 2/6] Fix cache instruction bug
  5. ---
  6. target/riscv/insn_trans/trans_rvi.c.inc | 18 +++++++++++-------
  7. 1 file changed, 11 insertions(+), 7 deletions(-)
  8. diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
  9. index 4d8f2668de..0152aba689 100644
  10. --- a/target/riscv/insn_trans/trans_rvi.c.inc
  11. +++ b/target/riscv/insn_trans/trans_rvi.c.inc
  12. @@ -1103,24 +1103,28 @@ static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
  13. static bool trans_cflush_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
  14. {
  15. - gen_helper_cflush_d_l1(cpu_gpr[a->rs1]);
  16. + if(a->rs1 != 0)
  17. + gen_helper_cflush_d_l1(cpu_gpr[a->rs1]);
  18. return true;
  19. }
  20. -static bool trans_cdiscard_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
  21. +static bool trans_cdiscard_d_l1(DisasContext *ctx, arg_cdiscard_d_l1 *a)
  22. {
  23. - gen_helper_cdiscard_d_l1(cpu_gpr[a->rs1]);
  24. + if(a->rs1 != 0)
  25. + gen_helper_cdiscard_d_l1(cpu_gpr[a->rs1]);
  26. return true;
  27. }
  28. -static bool trans_cflush_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
  29. +static bool trans_cflush_d_l2(DisasContext *ctx, arg_cflush_d_l2 *a)
  30. {
  31. - gen_helper_cflush_d_l2(cpu_gpr[a->rs1]);
  32. + if(a->rs1 != 0)
  33. + gen_helper_cflush_d_l2(cpu_gpr[a->rs1]);
  34. return true;
  35. }
  36. -static bool trans_cdiscard_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
  37. +static bool trans_cdiscard_d_l2(DisasContext *ctx, arg_cdiscard_d_l2 *a)
  38. {
  39. - gen_helper_cdiscard_d_l2(cpu_gpr[a->rs1]);
  40. + if(a->rs1 != 0)
  41. + gen_helper_cdiscard_d_l2(cpu_gpr[a->rs1]);
  42. return true;
  43. }
  44. \ No newline at end of file
  45. --
  46. 2.25.1