0001-Add-four-cache-csr-instruction.patch 3.7 KB

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  1. From 88a95b9fd65bae7c13a79bf3f99f9904bf33ca6c Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Wed, 29 Sep 2021 16:08:51 +0800
  4. Subject: [PATCH 1/6] Add four cache csr instruction
  5. ---
  6. target/riscv/helper.h | 7 +++++++
  7. target/riscv/insn32.decode | 9 +++++++++
  8. target/riscv/insn_trans/trans_rvi.c.inc | 24 ++++++++++++++++++++++++
  9. target/riscv/op_helper.c | 6 ++++++
  10. 4 files changed, 46 insertions(+)
  11. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  12. index a03014fe67..a20d092f44 100644
  13. --- a/target/riscv/helper.h
  14. +++ b/target/riscv/helper.h
  15. @@ -104,6 +104,13 @@ DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
  16. DEF_HELPER_2(csrr_i128, tl, env, int)
  17. DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
  18. DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
  19. +
  20. +/* Custom Cache CSR */
  21. +DEF_HELPER_1(cflush_d_l1, void, tl)
  22. +DEF_HELPER_1(cdiscard_d_l1, void, tl)
  23. +DEF_HELPER_1(cflush_d_l2, void, tl)
  24. +DEF_HELPER_1(cdiscard_d_l2, void, tl)
  25. +
  26. #ifndef CONFIG_USER_ONLY
  27. DEF_HELPER_1(sret, tl, env)
  28. DEF_HELPER_1(mret, tl, env)
  29. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  30. index d0253b8104..a2072e9322 100644
  31. --- a/target/riscv/insn32.decode
  32. +++ b/target/riscv/insn32.decode
  33. @@ -101,6 +101,9 @@
  34. # Formats 128:
  35. @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
  36. +# Custom Cache CSR
  37. +@csr_cache ............ ..... ... ..... ....... %rs1
  38. +
  39. # *** Privileged Instructions ***
  40. ecall 000000000000 00000 000 00000 1110011
  41. ebreak 000000000001 00000 000 00000 1110011
  42. @@ -111,6 +114,12 @@ wfi 0001000 00101 00000 000 00000 1110011
  43. sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
  44. sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
  45. +# *** Custom cache CSR ***
  46. +cflush_d_l1 111111000000 ..... 000 00000 1110011 @csr_cache
  47. +cdiscard_d_l1 111111000010 ..... 000 00000 1110011 @csr_cache
  48. +cflush_d_l2 111111000100 ..... 000 00000 1110011 @csr_cache
  49. +cdiscard_d_l2 111111000110 ..... 000 00000 1110011 @csr_cache
  50. +
  51. # *** RV32I Base Instruction Set ***
  52. lui .................... ..... 0110111 @u
  53. auipc .................... ..... 0010111 @u
  54. diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
  55. index c49dbec0eb..4d8f2668de 100644
  56. --- a/target/riscv/insn_trans/trans_rvi.c.inc
  57. +++ b/target/riscv/insn_trans/trans_rvi.c.inc
  58. @@ -1100,3 +1100,27 @@ static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
  59. ctx->zero, ctx->zero, mask, ctx->zero);
  60. }
  61. }
  62. +
  63. +static bool trans_cflush_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
  64. +{
  65. + gen_helper_cflush_d_l1(cpu_gpr[a->rs1]);
  66. + return true;
  67. +}
  68. +
  69. +static bool trans_cdiscard_d_l1(DisasContext *ctx, arg_cflush_d_l1 *a)
  70. +{
  71. + gen_helper_cdiscard_d_l1(cpu_gpr[a->rs1]);
  72. + return true;
  73. +}
  74. +
  75. +static bool trans_cflush_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
  76. +{
  77. + gen_helper_cflush_d_l2(cpu_gpr[a->rs1]);
  78. + return true;
  79. +}
  80. +
  81. +static bool trans_cdiscard_d_l2(DisasContext *ctx, arg_cflush_d_l1 *a)
  82. +{
  83. + gen_helper_cdiscard_d_l2(cpu_gpr[a->rs1]);
  84. + return true;
  85. +}
  86. \ No newline at end of file
  87. diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
  88. index 09f1f5185d..d4d3b734f2 100644
  89. --- a/target/riscv/op_helper.c
  90. +++ b/target/riscv/op_helper.c
  91. @@ -123,6 +123,12 @@ target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
  92. return int128_getlo(rv);
  93. }
  94. +void helper_cflush_d_l1(target_ulong rs1) {}
  95. +void helper_cdiscard_d_l1(target_ulong rs1) {}
  96. +void helper_cflush_d_l2(target_ulong rs1) {}
  97. +void helper_cdiscard_d_l2(target_ulong rs1) {}
  98. +
  99. +
  100. #ifndef CONFIG_USER_ONLY
  101. target_ulong helper_sret(CPURISCVState *env)
  102. --
  103. 2.25.1