0010-only-generate-strictly-aligned-code.patch 1.4 KB

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  1. From 6deaf5a014958a132eae634487783c7424ae57c2 Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Wed, 7 Dec 2022 18:36:45 -0800
  4. Subject: [PATCH 10/11] only generate strictly aligned code
  5. ---
  6. gcc/config/riscv/riscv.cc | 9 ++++++++-
  7. 1 file changed, 8 insertions(+), 1 deletion(-)
  8. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
  9. index 3baa05bd364..981dbf60bd1 100644
  10. --- a/gcc/config/riscv/riscv.cc
  11. +++ b/gcc/config/riscv/riscv.cc
  12. @@ -5046,9 +5046,12 @@ riscv_option_override (void)
  13. -m[no-]strict-align is left unspecified, heed -mtune's advice. */
  14. riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access
  15. || TARGET_STRICT_ALIGN);
  16. - if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
  17. + /* if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0
  18. && cpu->tune_param->slow_unaligned_access)
  19. target_flags |= MASK_STRICT_ALIGN;
  20. + */
  21. + /* for dubhe, it will not support unaligned mempry access */
  22. + target_flags |= MASK_STRICT_ALIGN;
  23. /* If the user hasn't specified a branch cost, use the processor's
  24. default. */
  25. @@ -5827,6 +5830,10 @@ riscv_asan_shadow_offset (void)
  26. #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
  27. #endif
  28. +/* For dubhe, it will not support unaligned memory access */
  29. +#undef TARGET_DEFAULT_TARGET_FLAGS
  30. +#define TARGET_DEFAULT_TARGET_FLAGS (MASK_STRICT_ALIGN)
  31. +
  32. struct gcc_target targetm = TARGET_INITIALIZER;
  33. #include "gt-riscv.h"
  34. --
  35. 2.25.1