0007-add-initial-dubhe-scheduling-model.patch 16 KB

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  1. From bda438df2f20aa476cfdfedca5ce017718a1eefd Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Thu, 1 Sep 2022 01:41:52 -0700
  4. Subject: [PATCH 07/11] add initial dubhe scheduling model
  5. ---
  6. gcc/config/riscv/bitmanip.md | 96 ++++++++++++++++++++++----------
  7. gcc/config/riscv/riscv-cores.def | 2 +
  8. gcc/config/riscv/riscv-opts.h | 3 +-
  9. gcc/config/riscv/riscv.cc | 23 +++++++-
  10. gcc/config/riscv/riscv.md | 47 ++--------------
  11. 5 files changed, 98 insertions(+), 73 deletions(-)
  12. diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
  13. index 0ab9ffe3c0b..86ac00d9a76 100644
  14. --- a/gcc/config/riscv/bitmanip.md
  15. +++ b/gcc/config/riscv/bitmanip.md
  16. @@ -62,7 +62,7 @@
  17. "TARGET_ZBA
  18. && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
  19. "sh%2add\t%0,%1,%3"
  20. - [(set_attr "type" "bitmanip")
  21. + [(set_attr "type" "bshiftadd")
  22. (set_attr "mode" "<X:MODE>")])
  23. (define_insn "*shNadduw"
  24. @@ -76,7 +76,7 @@
  25. && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
  26. && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
  27. "sh%2add.uw\t%0,%1,%4"
  28. - [(set_attr "type" "bitmanip")
  29. + [(set_attr "type" "bshiftadd")
  30. (set_attr "mode" "DI")])
  31. (define_insn "*add.uw"
  32. @@ -86,7 +86,7 @@
  33. (match_operand:DI 2 "register_operand" "r")))]
  34. "TARGET_64BIT && TARGET_ZBA"
  35. "add.uw\t%0,%1,%2"
  36. - [(set_attr "type" "bitmanip")
  37. + [(set_attr "type" "bopext")
  38. (set_attr "mode" "DI")])
  39. (define_insn "*slliuw"
  40. @@ -97,7 +97,7 @@
  41. "TARGET_64BIT && TARGET_ZBA
  42. && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
  43. "slli.uw\t%0,%1,%2"
  44. - [(set_attr "type" "bitmanip")
  45. + [(set_attr "type" "bopext")
  46. (set_attr "mode" "DI")])
  47. ;; ZBB extension.
  48. @@ -108,7 +108,7 @@
  49. (match_operand:X 2 "register_operand" "r")))]
  50. "TARGET_ZBB"
  51. "<insn>n\t%0,%2,%1"
  52. - [(set_attr "type" "bitmanip")
  53. + [(set_attr "type" "blogic_neg")
  54. (set_attr "mode" "<X:MODE>")])
  55. (define_insn "*xor_not<mode>"
  56. @@ -117,7 +117,7 @@
  57. (match_operand:X 2 "register_operand" "r"))))]
  58. "TARGET_ZBB"
  59. "xnor\t%0,%1,%2"
  60. - [(set_attr "type" "bitmanip")
  61. + [(set_attr "type" "blogic_neg")
  62. (set_attr "mode" "<X:MODE>")])
  63. (define_insn "<bitmanip_optab>si2"
  64. @@ -125,16 +125,17 @@
  65. (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))]
  66. "TARGET_ZBB"
  67. { return TARGET_64BIT ? "<bitmanip_insn>w\t%0,%1" : "<bitmanip_insn>\t%0,%1"; }
  68. - [(set_attr "type" "bitmanip")
  69. + [(set_attr "type" "bcount_bit")
  70. (set_attr "mode" "SI")])
  71. +
  72. (define_insn "*<bitmanip_optab>disi2"
  73. [(set (match_operand:DI 0 "register_operand" "=r")
  74. (sign_extend:DI
  75. (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))]
  76. "TARGET_64BIT && TARGET_ZBB"
  77. "<bitmanip_insn>w\t%0,%1"
  78. - [(set_attr "type" "bitmanip")
  79. + [(set_attr "type" "bcount_bit")
  80. (set_attr "mode" "SI")])
  81. (define_insn "<bitmanip_optab>di2"
  82. @@ -142,7 +143,7 @@
  83. (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))]
  84. "TARGET_64BIT && TARGET_ZBB"
  85. "<bitmanip_insn>\t%0,%1"
  86. - [(set_attr "type" "bitmanip")
  87. + [(set_attr "type" "bcount_bit")
  88. (set_attr "mode" "DI")])
  89. (define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
  90. @@ -155,6 +156,7 @@
  91. [(set_attr "type" "bitmanip,load")
  92. (set_attr "mode" "<GPR:MODE>")])
  93. +
  94. (define_insn "*extend<SHORT:mode><SUPERQI:mode>2_zbb"
  95. [(set (match_operand:SUPERQI 0 "register_operand" "=r,r")
  96. (sign_extend:SUPERQI
  97. @@ -183,7 +185,7 @@
  98. (match_operand:QI 2 "arith_operand" "rI")))]
  99. "TARGET_ZBB"
  100. { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
  101. - [(set_attr "type" "bitmanip")])
  102. + [(set_attr "type" "brorate")])
  103. (define_insn "rotrdi3"
  104. [(set (match_operand:DI 0 "register_operand" "=r")
  105. @@ -191,7 +193,7 @@
  106. (match_operand:QI 2 "arith_operand" "rI")))]
  107. "TARGET_64BIT && TARGET_ZBB"
  108. "ror%i2\t%0,%1,%2"
  109. - [(set_attr "type" "bitmanip")])
  110. + [(set_attr "type" "brorate")])
  111. (define_insn "rotrsi3_sext"
  112. [(set (match_operand:DI 0 "register_operand" "=r")
  113. @@ -199,7 +201,7 @@
  114. (match_operand:QI 2 "register_operand" "r"))))]
  115. "TARGET_64BIT && TARGET_ZBB"
  116. "rorw\t%0,%1,%2"
  117. - [(set_attr "type" "bitmanip")])
  118. + [(set_attr "type" "brorate")])
  119. (define_insn "rotlsi3"
  120. [(set (match_operand:SI 0 "register_operand" "=r")
  121. @@ -207,7 +209,7 @@
  122. (match_operand:QI 2 "register_operand" "r")))]
  123. "TARGET_ZBB"
  124. { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
  125. - [(set_attr "type" "bitmanip")])
  126. + [(set_attr "type" "brorate")])
  127. (define_insn "rotldi3"
  128. [(set (match_operand:DI 0 "register_operand" "=r")
  129. @@ -215,7 +217,7 @@
  130. (match_operand:QI 2 "register_operand" "r")))]
  131. "TARGET_64BIT && TARGET_ZBB"
  132. "rol\t%0,%1,%2"
  133. - [(set_attr "type" "bitmanip")])
  134. + [(set_attr "type" "brorate")])
  135. (define_insn "rotlsi3_sext"
  136. [(set (match_operand:DI 0 "register_operand" "=r")
  137. @@ -223,14 +225,14 @@
  138. (match_operand:QI 2 "register_operand" "r"))))]
  139. "TARGET_64BIT && TARGET_ZBB"
  140. "rolw\t%0,%1,%2"
  141. - [(set_attr "type" "bitmanip")])
  142. + [(set_attr "type" "brorate")])
  143. (define_insn "bswap<mode>2"
  144. [(set (match_operand:X 0 "register_operand" "=r")
  145. (bswap:X (match_operand:X 1 "register_operand" "r")))]
  146. "TARGET_64BIT && TARGET_ZBB"
  147. "rev8\t%0,%1"
  148. - [(set_attr "type" "bitmanip")])
  149. + [(set_attr "type" "bperm")])
  150. (define_insn "<bitmanip_optab><mode>3"
  151. [(set (match_operand:X 0 "register_operand" "=r")
  152. @@ -238,7 +240,7 @@
  153. (match_operand:X 2 "register_operand" "r")))]
  154. "TARGET_ZBB"
  155. "<bitmanip_insn>\t%0,%1,%2"
  156. - [(set_attr "type" "bitmanip")])
  157. + [(set_attr "type" "bcount_bit")])
  158. ;; ZBS extension.
  159. @@ -249,7 +251,7 @@
  160. (match_operand:X 1 "register_operand" "r")))]
  161. "TARGET_ZBS"
  162. "bset\t%0,%1,%2"
  163. - [(set_attr "type" "bitmanip")])
  164. + [(set_attr "type" "bsbit")])
  165. (define_insn "*bset<mode>_mask"
  166. [(set (match_operand:X 0 "register_operand" "=r")
  167. @@ -260,7 +262,7 @@
  168. (match_operand:X 1 "register_operand" "r")))]
  169. "TARGET_ZBS"
  170. "bset\t%0,%1,%2"
  171. - [(set_attr "type" "bitmanip")])
  172. + [(set_attr "type" "bsbit")])
  173. (define_insn "*bset<mode>_1"
  174. [(set (match_operand:X 0 "register_operand" "=r")
  175. @@ -268,7 +270,7 @@
  176. (match_operand:QI 1 "register_operand" "r")))]
  177. "TARGET_ZBS"
  178. "bset\t%0,x0,%1"
  179. - [(set_attr "type" "bitmanip")])
  180. + [(set_attr "type" "bsbit")])
  181. (define_insn "*bset<mode>_1_mask"
  182. [(set (match_operand:X 0 "register_operand" "=r")
  183. @@ -278,7 +280,7 @@
  184. (match_operand 2 "<X:shiftm1>" "i")) 0)))]
  185. "TARGET_ZBS"
  186. "bset\t%0,x0,%1"
  187. - [(set_attr "type" "bitmanip")])
  188. + [(set_attr "type" "bsbit")])
  189. (define_insn "*bseti<mode>"
  190. [(set (match_operand:X 0 "register_operand" "=r")
  191. @@ -286,7 +288,7 @@
  192. (match_operand 2 "single_bit_mask_operand" "i")))]
  193. "TARGET_ZBS"
  194. "bseti\t%0,%1,%S2"
  195. - [(set_attr "type" "bitmanip")])
  196. + [(set_attr "type" "bsbit")])
  197. (define_insn "*bclr<mode>"
  198. [(set (match_operand:X 0 "register_operand" "=r")
  199. @@ -295,7 +297,7 @@
  200. (match_operand:X 1 "register_operand" "r")))]
  201. "TARGET_ZBS"
  202. "bclr\t%0,%1,%2"
  203. - [(set_attr "type" "bitmanip")])
  204. + [(set_attr "type" "bsbit")])
  205. (define_insn "*bclri<mode>"
  206. [(set (match_operand:X 0 "register_operand" "=r")
  207. @@ -303,7 +305,7 @@
  208. (match_operand 2 "not_single_bit_mask_operand" "i")))]
  209. "TARGET_ZBS"
  210. "bclri\t%0,%1,%T2"
  211. - [(set_attr "type" "bitmanip")])
  212. + [(set_attr "type" "bsbit")])
  213. (define_insn "*binv<mode>"
  214. [(set (match_operand:X 0 "register_operand" "=r")
  215. @@ -312,7 +314,7 @@
  216. (match_operand:X 1 "register_operand" "r")))]
  217. "TARGET_ZBS"
  218. "binv\t%0,%1,%2"
  219. - [(set_attr "type" "bitmanip")])
  220. + [(set_attr "type" "bsbit")])
  221. (define_insn "*binvi<mode>"
  222. [(set (match_operand:X 0 "register_operand" "=r")
  223. @@ -320,7 +322,7 @@
  224. (match_operand 2 "single_bit_mask_operand" "i")))]
  225. "TARGET_ZBS"
  226. "binvi\t%0,%1,%S2"
  227. - [(set_attr "type" "bitmanip")])
  228. + [(set_attr "type" "bsbit")])
  229. (define_insn "*bext<mode>"
  230. [(set (match_operand:X 0 "register_operand" "=r")
  231. @@ -330,7 +332,7 @@
  232. (match_operand:QI 2 "register_operand" "r"))))]
  233. "TARGET_ZBS"
  234. "bext\t%0,%1,%2"
  235. - [(set_attr "type" "bitmanip")])
  236. + [(set_attr "type" "bsbit")])
  237. (define_insn "*bexti"
  238. [(set (match_operand:X 0 "register_operand" "=r")
  239. @@ -339,4 +341,42 @@
  240. (match_operand 2 "immediate_operand" "i")))]
  241. "TARGET_ZBS"
  242. "bexti\t%0,%1,%2"
  243. - [(set_attr "type" "bitmanip")])
  244. + [(set_attr "type" "bopext")])
  245. +
  246. +(define_insn "riscv_orc_b"
  247. + [(set (match_operand:SI 0 "register_operand" "=r")
  248. + (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
  249. + "TARGET_ZBB"
  250. + "orc.b\t%0,%1,%2"
  251. + [(set_attr "type" "bperm")])
  252. +
  253. +(define_insn "riscv_rev8"
  254. + [(set (match_operand:SI 0 "register_operand" "=r")
  255. + (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
  256. + "TARGET_ZBB"
  257. + "rev8\t%0,%1,%2"
  258. + [(set_attr "type" "bperm")])
  259. +
  260. +(define_insn "riscv_clmul"
  261. + [(set (match_operand:SI 0 "register_operand" "=r")
  262. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  263. + (match_operand:SI 2 "register_operand" "r"))))]
  264. + "TARGET_ZBC"
  265. + "clmul\t%0,%1,%2"
  266. + [(set_attr "type" "bclmul")])
  267. +
  268. +(define_insn "riscv_clmulh"
  269. + [(set (match_operand:SI 0 "register_operand" "=r")
  270. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  271. + (match_operand:SI 2 "register_operand" "r"))))]
  272. + "TARGET_ZBC"
  273. + "clmulh\t%0,%1,%2"
  274. + [(set_attr "type" "bclmul")])
  275. +
  276. +(define_insn "riscv_clmulr"
  277. + [(set (match_operand:SI 0 "register_operand" "=r")
  278. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  279. + (match_operand:SI 2 "register_operand" "r"))))]
  280. + "TARGET_ZBC"
  281. + "clmulr\t%0,%1,%2"
  282. + [(set_attr "type" "bclmul")])
  283. \ No newline at end of file
  284. diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
  285. index ecb5e213d98..051c9c5d05f 100644
  286. --- a/gcc/config/riscv/riscv-cores.def
  287. +++ b/gcc/config/riscv/riscv-cores.def
  288. @@ -45,5 +45,7 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series")
  289. RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
  290. RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
  291. +RISCV_CORE("starfive-dubhe", "rv64imafdc", "starfive-dubhe-series")
  292. +
  293. #undef RISCV_CORE
  294. diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
  295. index 15bb5e76854..fcb1aaa4ba1 100644
  296. --- a/gcc/config/riscv/riscv-opts.h
  297. +++ b/gcc/config/riscv/riscv-opts.h
  298. @@ -52,7 +52,8 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
  299. /* Keep this list in sync with define_attr "tune" in riscv.md. */
  300. enum riscv_microarchitecture_type {
  301. generic,
  302. - sifive_7
  303. + sifive_7,
  304. + starfive_dubhe
  305. };
  306. extern enum riscv_microarchitecture_type riscv_microarchitecture;
  307. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
  308. index ec7030f6c2e..3baa05bd364 100644
  309. --- a/gcc/config/riscv/riscv.cc
  310. +++ b/gcc/config/riscv/riscv.cc
  311. @@ -301,6 +301,19 @@ static const struct riscv_tune_param sifive_7_tune_info = {
  312. true, /* slow_unaligned_access */
  313. };
  314. +/* Costs to use when optimizing for dubhe. */
  315. +static const struct riscv_tune_param starfive_dubhe_tune_info = {
  316. + {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* fp_add */
  317. + {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* fp_mul */
  318. + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
  319. + {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* int_mul */
  320. + {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
  321. + 8, /* issue_rate */
  322. + 1, /* branch_cost */
  323. + 3, /* memory_cost */
  324. + true, /* slow_unaligned_access */
  325. +};
  326. +
  327. /* Costs to use when optimizing for T-HEAD c906. */
  328. static const struct riscv_tune_param thead_c906_tune_info = {
  329. {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
  330. @@ -327,6 +340,7 @@ static const struct riscv_tune_param optimize_size_tune_info = {
  331. false, /* slow_unaligned_access */
  332. };
  333. +
  334. static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
  335. static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
  336. @@ -361,7 +375,7 @@ static const struct riscv_tune_info riscv_tune_info_table[] = {
  337. { "rocket", generic, &rocket_tune_info },
  338. { "sifive-3-series", generic, &rocket_tune_info },
  339. { "sifive-5-series", generic, &rocket_tune_info },
  340. - { "sifive-7-series", sifive_7, &sifive_7_tune_info },
  341. + { "starfive-dubhe-series", starfive_dubhe, &starfive_dubhe_tune_info },
  342. { "thead-c906", generic, &thead_c906_tune_info },
  343. { "size", generic, &optimize_size_tune_info },
  344. };
  345. @@ -4763,12 +4777,15 @@ riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1,
  346. && (class1 == FP_REGS) != (class2 == FP_REGS));
  347. }
  348. -/* Implement TARGET_REGISTER_MOVE_COST. */
  349. -
  350. static int
  351. riscv_register_move_cost (machine_mode mode,
  352. reg_class_t from, reg_class_t to)
  353. {
  354. + /* do not move between fp and int registers. */
  355. + if (from == FP_REGS && to == GR_REGS || from == GR_REGS && to == FP_REGS)
  356. + return 20;
  357. +
  358. +
  359. return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2;
  360. }
  361. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
  362. index e56979ca800..1bcc6d49391 100644
  363. --- a/gcc/config/riscv/riscv.md
  364. +++ b/gcc/config/riscv/riscv.md
  365. @@ -169,10 +169,12 @@
  366. ;; nop no operation
  367. ;; ghost an instruction that produces no real code
  368. ;; bitmanip bit manipulation instructions
  369. +;;
  370. (define_attr "type"
  371. "unknown,branch,jump,call,load,fpload,store,fpstore,
  372. mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
  373. - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate"
  374. + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,
  375. + bopext,bshiftadd,brorate,blogic_neg,bminmax,bcount_bit,bclmul,bsbit,bperm"
  376. (cond [(eq_attr "got" "load") (const_string "load")
  377. ;; If a doubleword move uses these expensive instructions,
  378. @@ -254,7 +256,7 @@
  379. ;; Microarchitectures we know how to tune for.
  380. ;; Keep this in sync with enum riscv_microarchitecture.
  381. (define_attr "tune"
  382. - "generic,sifive_7"
  383. + "generic,sifive_7, starfive_dubhe"
  384. (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
  385. ;; Describe a user's asm statement.
  386. @@ -308,7 +310,7 @@
  387. ;; instruction.
  388. (define_mode_attr size [(QI "b") (HI "h")])
  389. -;; Mode attributes for loads.
  390. +;; Mode attriutes for loads.
  391. (define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (SF "flw") (DF "fld")])
  392. ;; Instruction names for integer loads that aren't explicitly sign or zero
  393. @@ -2767,44 +2769,6 @@
  394. [(set_attr "length" "0")]
  395. )
  396. -(define_insn "riscv_orc_b"
  397. - [(set (match_operand:SI 0 "register_operand" "=r")
  398. - (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
  399. - "TARGET_ZBB"
  400. - "orc.b\t%0,%1,%2"
  401. - [(set_attr "type" "bitmanip")])
  402. -
  403. -(define_insn "riscv_rev8"
  404. - [(set (match_operand:SI 0 "register_operand" "=r")
  405. - (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
  406. - "TARGET_ZBB"
  407. - "rev8\t%0,%1,%2"
  408. - [(set_attr "type" "bitmanip")])
  409. -
  410. -(define_insn "riscv_clmul"
  411. - [(set (match_operand:SI 0 "register_operand" "=r")
  412. - (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  413. - (match_operand:SI 2 "register_operand" "r"))))]
  414. - "TARGET_ZBC"
  415. - "clmul\t%0,%1,%2"
  416. - [(set_attr "type" "bitmanip")])
  417. -
  418. -(define_insn "riscv_clmulh"
  419. - [(set (match_operand:SI 0 "register_operand" "=r")
  420. - (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  421. - (match_operand:SI 2 "register_operand" "r"))))]
  422. - "TARGET_ZBC"
  423. - "clmulh\t%0,%1,%2"
  424. - [(set_attr "type" "bitmanip")])
  425. -
  426. -(define_insn "riscv_clmulr"
  427. - [(set (match_operand:SI 0 "register_operand" "=r")
  428. - (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  429. - (match_operand:SI 2 "register_operand" "r"))))]
  430. - "TARGET_ZBC"
  431. - "clmulr\t%0,%1,%2"
  432. - [(set_attr "type" "bitmanip")])
  433. -
  434. ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
  435. ;; 32-bit target when using -mtune=sifive-7-series. The first sched pass
  436. ;; runs before register elimination, and we have a non-obvious dependency
  437. @@ -2907,3 +2871,4 @@
  438. (include "pic.md")
  439. (include "generic.md")
  440. (include "sifive-7.md")
  441. +(include "starfive-dubhe.md")
  442. --
  443. 2.25.1