0006-merge-b-extension-changes.patch 10 KB

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  1. From fb72ef1b706a2dd0079a2bebd301f9503f5d2893 Mon Sep 17 00:00:00 2001
  2. From: "max.ma" <max.ma@starfivetech.com>
  3. Date: Thu, 7 Jul 2022 00:30:21 -0700
  4. Subject: [PATCH 06/11] merge b extension changes
  5. ---
  6. gcc/common/config/riscv/riscv-common.cc | 17 +++++++++--
  7. gcc/config/riscv/riscv-builtins.cc | 10 +++++++
  8. gcc/config/riscv/riscv-ftypes.def | 2 ++
  9. gcc/config/riscv/riscv.cc | 34 +++++++++++++++++++++-
  10. gcc/config/riscv/riscv.h | 9 ++----
  11. gcc/config/riscv/riscv.md | 38 +++++++++++++++++++++++++
  12. gcc/config/riscv/riscv.opt | 2 ++
  13. 7 files changed, 103 insertions(+), 9 deletions(-)
  14. diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
  15. index 1501242e296..967c28d0498 100644
  16. --- a/gcc/common/config/riscv/riscv-common.cc
  17. +++ b/gcc/common/config/riscv/riscv-common.cc
  18. @@ -47,6 +47,10 @@ struct riscv_implied_info_t
  19. /* Implied ISA info, must end with NULL sentinel. */
  20. static const riscv_implied_info_t riscv_implied_info[] =
  21. {
  22. + {"b", "zbb"},
  23. + {"b", "zbs"},
  24. + {"b", "zba"},
  25. + {"b", "zbc"},
  26. {"d", "f"},
  27. {"f", "zicsr"},
  28. {"d", "zicsr"},
  29. @@ -149,6 +153,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
  30. {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
  31. {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
  32. + {"b", ISA_SPEC_CLASS_NONE, 1, 0},
  33. {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
  34. {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
  35. {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
  36. @@ -787,7 +792,14 @@ riscv_subset_list::parse_std_ext (const char *p)
  37. p = parsing_subset_version (subset, p, &major_version, &minor_version,
  38. /* std_ext_p= */ true, &explicit_version_p);
  39. -
  40. + if (std_ext == 'b')
  41. + {
  42. + add ("zba", major_version, minor_version, explicit_version_p, false);
  43. + add ("zbb", major_version, minor_version, explicit_version_p, false);
  44. + add ("zbc", major_version, minor_version, explicit_version_p, false);
  45. + add ("zbs", major_version, minor_version, explicit_version_p, false);
  46. + }
  47. + else
  48. add (subset, major_version, minor_version, explicit_version_p, false);
  49. }
  50. return p;
  51. @@ -1094,6 +1106,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
  52. {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
  53. {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
  54. + {"b", &gcc_options::x_target_flags, MASK_BITMANIP},
  55. {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
  56. {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
  57. {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},
  58. @@ -1304,4 +1317,4 @@ static const struct default_options riscv_option_optimization_table[] =
  59. #undef TARGET_HANDLE_OPTION
  60. #define TARGET_HANDLE_OPTION riscv_handle_option
  61. -struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
  62. +struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
  63. \ No newline at end of file
  64. diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
  65. index 0658f8d3047..d50876a26f7 100644
  66. --- a/gcc/config/riscv/riscv-builtins.cc
  67. +++ b/gcc/config/riscv/riscv-builtins.cc
  68. @@ -40,6 +40,7 @@ along with GCC; see the file COPYING3. If not see
  69. /* Macros to create an enumeration identifier for a function prototype. */
  70. #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
  71. #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
  72. +#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
  73. /* Classifies the prototype of a built-in function. */
  74. enum riscv_function_type {
  75. @@ -86,6 +87,8 @@ struct riscv_builtin_description {
  76. };
  77. AVAIL (hard_float, TARGET_HARD_FLOAT)
  78. +AVAIL (zbb, TARGET_ZBB)
  79. +AVAIL (zbc, TARGET_ZBC)
  80. /* Construct a riscv_builtin_description from the given arguments.
  81. @@ -119,6 +122,7 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
  82. /* Argument types. */
  83. #define RISCV_ATYPE_VOID void_type_node
  84. #define RISCV_ATYPE_USI unsigned_intSI_type_node
  85. +#define RISCV_ATYPE_SI intSI_type_node
  86. /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
  87. their associated RISCV_ATYPEs. */
  88. @@ -126,8 +130,14 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
  89. RISCV_ATYPE_##A
  90. #define RISCV_FTYPE_ATYPES1(A, B) \
  91. RISCV_ATYPE_##A, RISCV_ATYPE_##B
  92. +#define RISCV_FTYPE_ATYPES2(A, B, C) \
  93. + RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
  94. static const struct riscv_builtin_description riscv_builtins[] = {
  95. + DIRECT_BUILTIN (orc_b, RISCV_SI_FTYPE_SI, zbb),
  96. + DIRECT_BUILTIN (clmul, RISCV_SI_FTYPE_SI_SI, zbc),
  97. + DIRECT_BUILTIN (clmulh, RISCV_SI_FTYPE_SI_SI, zbc),
  98. + DIRECT_BUILTIN (clmulr, RISCV_SI_FTYPE_SI_SI, zbc),
  99. DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
  100. DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
  101. };
  102. diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
  103. index 2214c496f9b..edcfd44dacc 100644
  104. --- a/gcc/config/riscv/riscv-ftypes.def
  105. +++ b/gcc/config/riscv/riscv-ftypes.def
  106. @@ -28,3 +28,5 @@ along with GCC; see the file COPYING3. If not see
  107. DEF_RISCV_FTYPE (0, (USI))
  108. DEF_RISCV_FTYPE (1, (VOID, USI))
  109. +DEF_RISCV_FTYPE (1, (SI, SI))
  110. +DEF_RISCV_FTYPE (2, (SI, SI, SI))
  111. \ No newline at end of file
  112. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
  113. index ee756aab694..ec7030f6c2e 100644
  114. --- a/gcc/config/riscv/riscv.cc
  115. +++ b/gcc/config/riscv/riscv.cc
  116. @@ -415,6 +415,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
  117. /* Simply BSETI. */
  118. codes[0].code = UNKNOWN;
  119. codes[0].value = value;
  120. +
  121. + /* RISC-V sign-extends all 32bit values that life in a 32bit
  122. + register. To avoid paradoxes, we thus need to use the
  123. + sign-extended (negative) representation for the value, if we
  124. + want to build 0x80000000 in SImode. This will then expand
  125. + to an ADDI/LI instruction. */
  126. + if (mode == SImode && value == 0x80000000)
  127. + codes[0].value = -2147483648;
  128. +
  129. return 1;
  130. }
  131. @@ -2014,8 +2023,22 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  132. (TARGET_64BIT && (mode == DImode)))
  133. && (GET_CODE (XEXP (x, 0)) == ASHIFT)
  134. && REG_P (XEXP (XEXP (x, 0), 0))
  135. + && CONST_INT_P (XEXP (XEXP (x, 0), 0))
  136. + && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 0)), 1, 3))
  137. + {
  138. + *total = COSTS_N_INSNS (1);
  139. + return true;
  140. + }
  141. + /* Before strength-reduction, the shNadd can be expressed as the addition
  142. + of a multiplication with a power-of-two. If this case is not handled,
  143. + the strength-reduction in expmed.c will calculate an inflated cost. */
  144. + if (TARGET_ZBA
  145. + && ((!TARGET_64BIT && (mode == SImode)) ||
  146. + (TARGET_64BIT && (mode == DImode)))
  147. + && (GET_CODE (XEXP (x, 0)) == MULT)
  148. + && REG_P (XEXP (XEXP (x, 0), 0))
  149. && CONST_INT_P (XEXP (XEXP (x, 0), 1))
  150. - && IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1)), 1, 3))
  151. + && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3))
  152. {
  153. *total = COSTS_N_INSNS (1);
  154. return true;
  155. @@ -2044,6 +2067,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  156. if (!CONST_INT_P (and_rhs))
  157. break;
  158. + rtx ashift_lhs = XEXP (and_lhs, 0);
  159. rtx ashift_rhs = XEXP (and_lhs, 1);
  160. if (!CONST_INT_P (ashift_rhs)
  161. @@ -2131,6 +2155,14 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
  162. *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND);
  163. return false;
  164. + case BSWAP:
  165. + if (TARGET_ZBB)
  166. + {
  167. + *total = COSTS_N_INSNS (1);
  168. + return true;
  169. + }
  170. + return false;
  171. +
  172. case FLOAT:
  173. case UNSIGNED_FLOAT:
  174. case FIX:
  175. diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
  176. index 8a4d2cf7f85..045920b49cf 100644
  177. --- a/gcc/config/riscv/riscv.h
  178. +++ b/gcc/config/riscv/riscv.h
  179. @@ -528,13 +528,10 @@ enum reg_class
  180. (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \
  181. || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
  182. -/* If this is a single bit mask, then we can load it with bseti. But this
  183. - is not useful for any of the low 31 bits because we can use addi or lui
  184. - to load them. It is wrong for loading SImode 0x80000000 on rv64 because it
  185. - needs to be sign-extended. So we restrict this to the upper 32-bits
  186. - only. */
  187. +/* If this is a single bit mask, then we can load it with bseti. Special
  188. + handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */
  189. #define SINGLE_BIT_MASK_OPERAND(VALUE) \
  190. - (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32))
  191. + (pow2p_hwi (VALUE))
  192. /* Stack layout; function entry, exit and calling. */
  193. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
  194. index b3c5bce842a..e56979ca800 100644
  195. --- a/gcc/config/riscv/riscv.md
  196. +++ b/gcc/config/riscv/riscv.md
  197. @@ -2767,6 +2767,44 @@
  198. [(set_attr "length" "0")]
  199. )
  200. +(define_insn "riscv_orc_b"
  201. + [(set (match_operand:SI 0 "register_operand" "=r")
  202. + (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
  203. + "TARGET_ZBB"
  204. + "orc.b\t%0,%1,%2"
  205. + [(set_attr "type" "bitmanip")])
  206. +
  207. +(define_insn "riscv_rev8"
  208. + [(set (match_operand:SI 0 "register_operand" "=r")
  209. + (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
  210. + "TARGET_ZBB"
  211. + "rev8\t%0,%1,%2"
  212. + [(set_attr "type" "bitmanip")])
  213. +
  214. +(define_insn "riscv_clmul"
  215. + [(set (match_operand:SI 0 "register_operand" "=r")
  216. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  217. + (match_operand:SI 2 "register_operand" "r"))))]
  218. + "TARGET_ZBC"
  219. + "clmul\t%0,%1,%2"
  220. + [(set_attr "type" "bitmanip")])
  221. +
  222. +(define_insn "riscv_clmulh"
  223. + [(set (match_operand:SI 0 "register_operand" "=r")
  224. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  225. + (match_operand:SI 2 "register_operand" "r"))))]
  226. + "TARGET_ZBC"
  227. + "clmulh\t%0,%1,%2"
  228. + [(set_attr "type" "bitmanip")])
  229. +
  230. +(define_insn "riscv_clmulr"
  231. + [(set (match_operand:SI 0 "register_operand" "=r")
  232. + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
  233. + (match_operand:SI 2 "register_operand" "r"))))]
  234. + "TARGET_ZBC"
  235. + "clmulr\t%0,%1,%2"
  236. + [(set_attr "type" "bitmanip")])
  237. +
  238. ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
  239. ;; 32-bit target when using -mtune=sifive-7-series. The first sched pass
  240. ;; runs before register elimination, and we have a non-obvious dependency
  241. diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
  242. index 492aad12324..fa6d61fc66a 100644
  243. --- a/gcc/config/riscv/riscv.opt
  244. +++ b/gcc/config/riscv/riscv.opt
  245. @@ -136,6 +136,8 @@ Mask(64BIT)
  246. Mask(MUL)
  247. +Mask(BITMANIP)
  248. +
  249. Mask(ATOMIC)
  250. Mask(HARD_FLOAT)
  251. --
  252. 2.25.1