0001-add-Custom-CSR-instructions.patch 3.0 KB

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  1. From 51596716546e1ffa485bc2f202d3231177ceffc3 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Tue, 6 Dec 2022 19:39:16 -0800
  4. Subject: [PATCH 1/3] add Custom CSR instructions
  5. ---
  6. include/opcode/riscv-opc.h | 16 ++++++++++++++++
  7. opcodes/riscv-opc.c | 6 ++++++
  8. 2 files changed, 22 insertions(+)
  9. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
  10. index 06e3df0f5a..879eee8471 100644
  11. --- a/include/opcode/riscv-opc.h
  12. +++ b/include/opcode/riscv-opc.h
  13. @@ -267,6 +267,16 @@
  14. #define MASK_CSRRSI 0x707f
  15. #define MATCH_CSRRCI 0x7073
  16. #define MASK_CSRRCI 0x707f
  17. +/* Custom CSR instruction */
  18. +#define MATCH_CFLUSH_D_L1 0xfc000073
  19. +#define MASK_CFLUSH_D_L1 0xfff07fff
  20. +#define MATCH_CDISCARD_D_L1 0xfc200073
  21. +#define MASK_CDISCARD_D_L1 0xfff07fff
  22. +#define MATCH_CFLUSH_D_L2 0xfc400073
  23. +#define MASK_CFLUSH_D_L2 0xfff07fff
  24. +#define MATCH_CDISCARD_D_L2 0xfc600073
  25. +#define MASK_CDISCARD_D_L2 0xfff07fff
  26. +/**************************************/
  27. #define MATCH_FADD_S 0x53
  28. #define MASK_FADD_S 0xfe00007f
  29. #define MATCH_FSUB_S 0x8000053
  30. @@ -2905,6 +2915,12 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
  31. DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
  32. DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
  33. DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
  34. +/* Custom CSR instruction */
  35. +DECLARE_INSN(cflush_d_l1, MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1)
  36. +DECLARE_INSN(cdiscard_d_l1, MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1)
  37. +DECLARE_INSN(cflush_d_l2, MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2)
  38. +DECLARE_INSN(cdiscard_d_l2, MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2)
  39. +/*******************************************************************/
  40. DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
  41. DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
  42. DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
  43. diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
  44. index 0e691544f9..f4d1cda8b9 100644
  45. --- a/opcodes/riscv-opc.c
  46. +++ b/opcodes/riscv-opc.c
  47. @@ -929,6 +929,12 @@ const struct riscv_opcode riscv_opcodes[] =
  48. {"c.fswsp", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_DREF|INSN_4_BYTE },
  49. {"c.fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
  50. +/* Custom CSR instruction */
  51. +{"cflush.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L1, MASK_CFLUSH_D_L1, match_opcode, 0 },
  52. +{"cdiscard.d.l1", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L1, MASK_CDISCARD_D_L1, match_opcode, 0 },
  53. +{"cflush.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CFLUSH_D_L2, MASK_CFLUSH_D_L2, match_opcode, 0 },
  54. +{"cdiscard.d.l2", 0, INSN_CLASS_ZICSR, "s", MATCH_CDISCARD_D_L2, MASK_CDISCARD_D_L2, match_opcode, 0 },
  55. +/**********************************************************************************************************/
  56. /* Zicbom and Zicboz instructions. */
  57. {"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
  58. {"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
  59. --
  60. 2.25.1