123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051 |
- From 6a354df65631f859834b2ef5533501248996b2e7 Mon Sep 17 00:00:00 2001
- From: Kito Cheng <kito.cheng@sifive.com>
- Date: Tue, 20 Oct 2020 17:55:54 +0800
- Subject: [PATCH 091/107] target/riscv: rvb: sign-extend instructions
- Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- ---
- target/riscv/insn32.decode | 2 ++
- target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
- 2 files changed, 14 insertions(+)
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index 0d951f7f1a..531de51c63 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -694,6 +694,8 @@ fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
- clz 011000 000000 ..... 001 ..... 0010011 @r2
- ctz 011000 000001 ..... 001 ..... 0010011 @r2
- cpop 011000 000010 ..... 001 ..... 0010011 @r2
- +sext_b 011000 000100 ..... 001 ..... 0010011 @r2
- +sext_h 011000 000101 ..... 001 ..... 0010011 @r2
-
- andn 0100000 .......... 111 ..... 0110011 @r
- orn 0100000 .......... 110 ..... 0110011 @r
- diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
- index 2aa4515fe3..1496996a66 100644
- --- a/target/riscv/insn_trans/trans_rvb.c.inc
- +++ b/target/riscv/insn_trans/trans_rvb.c.inc
- @@ -95,6 +95,18 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
- return gen_arith(ctx, a, tcg_gen_umax_tl);
- }
-
- +static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_unary(ctx, a, tcg_gen_ext8s_tl);
- +}
- +
- +static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
- +{
- + REQUIRE_EXT(ctx, RVB);
- + return gen_unary(ctx, a, tcg_gen_ext16s_tl);
- +}
- +
- /* RV64-only instructions */
- #ifdef TARGET_RISCV64
-
- --
- 2.33.1
|