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- From 1e98c970b4a3f3e359edd1eb883774b977232019 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Tue, 6 Oct 2020 23:48:24 +0800
- Subject: [PATCH 075/107] target/riscv: rvv-1.0: set mstatus.SD bit when
- writing vector CSRs
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
- ---
- target/riscv/csr.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
- diff --git a/target/riscv/csr.c b/target/riscv/csr.c
- index b932e28bbf..900c2fa50a 100644
- --- a/target/riscv/csr.c
- +++ b/target/riscv/csr.c
- @@ -293,7 +293,7 @@ static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
- if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- - env->mstatus |= MSTATUS_VS;
- + env->mstatus |= MSTATUS_VS | MSTATUS_SD;
- #endif
-
- env->vxrm = val;
- @@ -312,7 +312,7 @@ static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
- if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- - env->mstatus |= MSTATUS_VS;
- + env->mstatus |= MSTATUS_VS | MSTATUS_SD;
- #endif
-
- env->vxsat = val;
- @@ -331,7 +331,7 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
- if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- - env->mstatus |= MSTATUS_VS;
- + env->mstatus |= MSTATUS_VS | MSTATUS_SD;
- #endif
-
- /*
- @@ -354,7 +354,7 @@ static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
- if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
- return -RISCV_EXCP_ILLEGAL_INST;
- }
- - env->mstatus |= MSTATUS_VS;
- + env->mstatus |= MSTATUS_VS | MSTATUS_SD;
- #endif
-
- env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
- --
- 2.33.1
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