0051-target-riscv-rvv-1.0-narrowing-integer-right-shift-i.patch 10 KB

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  1. From 2e5f58888215b897d65552d1ecbca7110724fb16 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 2 Jul 2020 12:17:33 +0800
  4. Subject: [PATCH 051/107] target/riscv: rvv-1.0: narrowing integer right shift
  5. instructions
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/helper.h | 24 ++++++++++----------
  10. target/riscv/insn32.decode | 12 +++++-----
  11. target/riscv/insn_trans/trans_rvv.c.inc | 30 ++++++++++++-------------
  12. target/riscv/vector_helper.c | 24 ++++++++++----------
  13. 4 files changed, 45 insertions(+), 45 deletions(-)
  14. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  15. index 9ff330e6d8..b582fe8720 100644
  16. --- a/target/riscv/helper.h
  17. +++ b/target/riscv/helper.h
  18. @@ -426,18 +426,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  19. DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  20. DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
  21. -DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  22. -DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  23. -DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  24. -DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  25. -DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  26. -DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  27. -DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  28. -DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  29. -DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  30. -DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  31. -DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  32. -DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  33. +DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
  34. +DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
  35. +DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
  36. +DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
  37. +DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
  38. +DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
  39. +DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32)
  40. +DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32)
  41. +DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32)
  42. +DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32)
  43. +DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32)
  44. +DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32)
  45. DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  46. DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  47. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  48. index 462ec504b3..d3d70b47c1 100644
  49. --- a/target/riscv/insn32.decode
  50. +++ b/target/riscv/insn32.decode
  51. @@ -381,12 +381,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
  52. vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
  53. vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
  54. vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
  55. -vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
  56. -vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
  57. -vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
  58. -vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
  59. -vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
  60. -vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
  61. +vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
  62. +vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
  63. +vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
  64. +vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
  65. +vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
  66. +vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
  67. vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
  68. vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
  69. vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
  70. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  71. index 6ffbf5ea08..ebbb415c17 100644
  72. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  73. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  74. @@ -1920,7 +1920,7 @@ GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
  75. GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
  76. /* Vector Narrowing Integer Right Shift Instructions */
  77. -static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
  78. +static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a)
  79. {
  80. return require_rvv(s) &&
  81. vext_check_isa_ill(s) &&
  82. @@ -1928,10 +1928,10 @@ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
  83. }
  84. /* OPIVV with NARROW */
  85. -#define GEN_OPIVV_NARROW_TRANS(NAME) \
  86. +#define GEN_OPIWV_NARROW_TRANS(NAME) \
  87. static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  88. { \
  89. - if (opivv_narrow_check(s, a)) { \
  90. + if (opiwv_narrow_check(s, a)) { \
  91. uint32_t data = 0; \
  92. static gen_helper_gvec_4_ptr * const fns[3] = { \
  93. gen_helper_##NAME##_b, \
  94. @@ -1953,10 +1953,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  95. } \
  96. return false; \
  97. }
  98. -GEN_OPIVV_NARROW_TRANS(vnsra_vv)
  99. -GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
  100. +GEN_OPIWV_NARROW_TRANS(vnsra_wv)
  101. +GEN_OPIWV_NARROW_TRANS(vnsrl_wv)
  102. -static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
  103. +static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a)
  104. {
  105. return require_rvv(s) &&
  106. vext_check_isa_ill(s) &&
  107. @@ -1964,10 +1964,10 @@ static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
  108. }
  109. /* OPIVX with NARROW */
  110. -#define GEN_OPIVX_NARROW_TRANS(NAME) \
  111. +#define GEN_OPIWX_NARROW_TRANS(NAME) \
  112. static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  113. { \
  114. - if (opivx_narrow_check(s, a)) { \
  115. + if (opiwx_narrow_check(s, a)) { \
  116. static gen_helper_opivx * const fns[3] = { \
  117. gen_helper_##NAME##_b, \
  118. gen_helper_##NAME##_h, \
  119. @@ -1978,14 +1978,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  120. return false; \
  121. }
  122. -GEN_OPIVX_NARROW_TRANS(vnsra_vx)
  123. -GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
  124. +GEN_OPIWX_NARROW_TRANS(vnsra_wx)
  125. +GEN_OPIWX_NARROW_TRANS(vnsrl_wx)
  126. -/* OPIVI with NARROW */
  127. -#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \
  128. +/* OPIWI with NARROW */
  129. +#define GEN_OPIWI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \
  130. static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  131. { \
  132. - if (opivx_narrow_check(s, a)) { \
  133. + if (opiwx_narrow_check(s, a)) { \
  134. static gen_helper_opivx * const fns[3] = { \
  135. gen_helper_##OPIVX##_b, \
  136. gen_helper_##OPIVX##_h, \
  137. @@ -1997,8 +1997,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  138. return false; \
  139. }
  140. -GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx)
  141. -GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx)
  142. +GEN_OPIWI_NARROW_TRANS(vnsra_wi, IMM_ZX, vnsra_wx)
  143. +GEN_OPIWI_NARROW_TRANS(vnsrl_wi, IMM_ZX, vnsrl_wx)
  144. /* Vector Integer Comparison Instructions */
  145. /*
  146. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  147. index f351743114..19542c9f5a 100644
  148. --- a/target/riscv/vector_helper.c
  149. +++ b/target/riscv/vector_helper.c
  150. @@ -1373,18 +1373,18 @@ GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f)
  151. GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f)
  152. /* Vector Narrowing Integer Right Shift Instructions */
  153. -GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
  154. -GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
  155. -GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
  156. -GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf)
  157. -GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f)
  158. -GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f)
  159. -GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
  160. -GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
  161. -GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
  162. -GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf)
  163. -GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f)
  164. -GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f)
  165. +GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
  166. +GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
  167. +GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
  168. +GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf)
  169. +GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f)
  170. +GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f)
  171. +GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
  172. +GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
  173. +GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
  174. +GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf)
  175. +GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f)
  176. +GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f)
  177. /* Vector Integer Comparison Instructions */
  178. #define DO_MSEQ(N, M) (N == M)
  179. --
  180. 2.33.1