0050-target-riscv-rvv-1.0-integer-add-with-carry-subtract.patch 7.2 KB

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  1. From 7435c8b5574ec0d31b3db9730945057dbc1dee9b Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 30 Jul 2020 21:32:13 +0800
  4. Subject: [PATCH 050/107] target/riscv: rvv-1.0: integer
  5. add-with-carry/subtract-with-borrow
  6. * Only do carry-in or borrow-in if is masked (vm=0).
  7. * Remove clear function from helper functions as the tail elements
  8. are unchanged in RVV 1.0.
  9. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  10. ---
  11. target/riscv/insn32.decode | 20 ++++++++++----------
  12. target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
  13. target/riscv/vector_helper.c | 20 ++++++--------------
  14. 3 files changed, 17 insertions(+), 25 deletions(-)
  15. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  16. index 3806810f4f..462ec504b3 100644
  17. --- a/target/riscv/insn32.decode
  18. +++ b/target/riscv/insn32.decode
  19. @@ -353,16 +353,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
  20. vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
  21. vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
  22. vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
  23. -vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
  24. -vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
  25. -vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
  26. -vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
  27. -vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
  28. -vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
  29. -vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
  30. -vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
  31. -vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
  32. -vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
  33. +vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
  34. +vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
  35. +vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
  36. +vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
  37. +vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
  38. +vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
  39. +vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
  40. +vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
  41. +vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
  42. +vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
  43. vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
  44. vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
  45. vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
  46. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  47. index 75a5d6f7a5..6ffbf5ea08 100644
  48. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  49. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  50. @@ -1774,7 +1774,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  51. /*
  52. * For vadc and vsbc, an illegal instruction exception is raised if the
  53. - * destination vector register is v0 and LMUL > 1. (Section 12.3)
  54. + * destination vector register is v0 and LMUL > 1. (Section 12.4)
  55. */
  56. static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
  57. {
  58. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  59. index 55b55e5b59..f351743114 100644
  60. --- a/target/riscv/vector_helper.c
  61. +++ b/target/riscv/vector_helper.c
  62. @@ -1153,7 +1153,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
  63. for (i = 0; i < vl; i++) { \
  64. ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
  65. ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
  66. - uint8_t carry = vext_elem_mask(v0, i); \
  67. + ETYPE carry = vext_elem_mask(v0, i); \
  68. \
  69. *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
  70. } \
  71. @@ -1178,7 +1178,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
  72. \
  73. for (i = 0; i < vl; i++) { \
  74. ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
  75. - uint8_t carry = vext_elem_mask(v0, i); \
  76. + ETYPE carry = vext_elem_mask(v0, i); \
  77. \
  78. *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
  79. } \
  80. @@ -1203,19 +1203,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
  81. CPURISCVState *env, uint32_t desc) \
  82. { \
  83. uint32_t vl = env->vl; \
  84. - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
  85. + uint32_t vm = vext_vm(desc); \
  86. uint32_t i; \
  87. \
  88. for (i = 0; i < vl; i++) { \
  89. ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
  90. ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
  91. - uint8_t carry = vext_elem_mask(v0, i); \
  92. - \
  93. + ETYPE carry = !vm && vext_elem_mask(v0, i); \
  94. vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
  95. } \
  96. - for (; i < vlmax; i++) { \
  97. - vext_set_elem_mask(vd, i, 0); \
  98. - } \
  99. }
  100. GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
  101. @@ -1233,19 +1229,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
  102. void *vs2, CPURISCVState *env, uint32_t desc) \
  103. { \
  104. uint32_t vl = env->vl; \
  105. - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
  106. + uint32_t vm = vext_vm(desc); \
  107. uint32_t i; \
  108. \
  109. for (i = 0; i < vl; i++) { \
  110. ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
  111. - uint8_t carry = vext_elem_mask(v0, i); \
  112. - \
  113. + ETYPE carry = !vm && vext_elem_mask(v0, i); \
  114. vext_set_elem_mask(vd, i, \
  115. DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
  116. } \
  117. - for (; i < vlmax; i++) { \
  118. - vext_set_elem_mask(vd, i, 0); \
  119. - } \
  120. }
  121. GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC)
  122. --
  123. 2.33.1