0049-target-riscv-rvv-1.0-single-width-bit-shift-instruct.patch 1.4 KB

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  1. From 249b8790558e018fdf8c1d3c585222e00ac08afd Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 20 Jul 2020 22:36:34 +0800
  4. Subject: [PATCH 049/107] target/riscv: rvv-1.0: single-width bit shift
  5. instructions
  6. Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
  7. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  8. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  9. ---
  10. target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
  11. 1 file changed, 3 insertions(+), 3 deletions(-)
  12. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  13. index d3b71a2bb2..75a5d6f7a5 100644
  14. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  15. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  16. @@ -1915,9 +1915,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
  17. GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
  18. GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
  19. -GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
  20. -GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
  21. -GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
  22. +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli)
  23. +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
  24. +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
  25. /* Vector Narrowing Integer Right Shift Instructions */
  26. static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
  27. --
  28. 2.33.1