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- From 249b8790558e018fdf8c1d3c585222e00ac08afd Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Mon, 20 Jul 2020 22:36:34 +0800
- Subject: [PATCH 049/107] target/riscv: rvv-1.0: single-width bit shift
- instructions
- Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- ---
- target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index d3b71a2bb2..75a5d6f7a5 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -1915,9 +1915,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
- GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
- GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-
- -GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
- -GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
- -GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
- +GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli)
- +GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
- +GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
-
- /* Vector Narrowing Integer Right Shift Instructions */
- static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
- --
- 2.33.1
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