0048-target-riscv-rvv-1.0-single-width-averaging-add-and-.patch 8.5 KB

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  1. From 1a086615faea4f46c8ba625b72c0b6e886536989 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 30 Jul 2020 21:23:01 +0800
  4. Subject: [PATCH 048/107] target/riscv: rvv-1.0: single-width averaging add and
  5. subtract instructions
  6. Add the following instructions:
  7. * vaaddu.vv
  8. * vaaddu.vx
  9. * vasubu.vv
  10. * vasubu.vx
  11. Remove the following instructions:
  12. * vadd.vi
  13. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  14. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  15. ---
  16. target/riscv/helper.h | 16 ++++++
  17. target/riscv/insn32.decode | 13 +++--
  18. target/riscv/insn_trans/trans_rvv.c.inc | 5 +-
  19. target/riscv/vector_helper.c | 74 +++++++++++++++++++++++++
  20. 4 files changed, 102 insertions(+), 6 deletions(-)
  21. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  22. index 6d67b67311..9ff330e6d8 100644
  23. --- a/target/riscv/helper.h
  24. +++ b/target/riscv/helper.h
  25. @@ -723,18 +723,34 @@ DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  26. DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  27. DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  28. DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
  29. +DEF_HELPER_6(vaaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  30. +DEF_HELPER_6(vaaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  31. +DEF_HELPER_6(vaaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  32. +DEF_HELPER_6(vaaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
  33. DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  34. DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  35. DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  36. DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
  37. +DEF_HELPER_6(vasubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  38. +DEF_HELPER_6(vasubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  39. +DEF_HELPER_6(vasubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  40. +DEF_HELPER_6(vasubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
  41. DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  42. DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  43. DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  44. DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
  45. +DEF_HELPER_6(vaaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  46. +DEF_HELPER_6(vaaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  47. +DEF_HELPER_6(vaaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  48. +DEF_HELPER_6(vaaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
  49. DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  50. DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  51. DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  52. DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
  53. +DEF_HELPER_6(vasubu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  54. +DEF_HELPER_6(vasubu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  55. +DEF_HELPER_6(vasubu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  56. +DEF_HELPER_6(vasubu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
  57. DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  58. DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  59. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  60. index 3c735b866d..3806810f4f 100644
  61. --- a/target/riscv/insn32.decode
  62. +++ b/target/riscv/insn32.decode
  63. @@ -468,11 +468,14 @@ vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
  64. vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
  65. vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
  66. vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
  67. -vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm
  68. -vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm
  69. -vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm
  70. -vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm
  71. -vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
  72. +vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
  73. +vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
  74. +vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
  75. +vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
  76. +vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
  77. +vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
  78. +vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
  79. +vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
  80. vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
  81. vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
  82. vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
  83. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  84. index 58f0edc031..d3b71a2bb2 100644
  85. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  86. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  87. @@ -2237,10 +2237,13 @@ GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
  88. /* Vector Single-Width Averaging Add and Subtract */
  89. GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
  90. +GEN_OPIVV_TRANS(vaaddu_vv, opivv_check)
  91. GEN_OPIVV_TRANS(vasub_vv, opivv_check)
  92. +GEN_OPIVV_TRANS(vasubu_vv, opivv_check)
  93. GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
  94. +GEN_OPIVX_TRANS(vaaddu_vx, opivx_check)
  95. GEN_OPIVX_TRANS(vasub_vx, opivx_check)
  96. -GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
  97. +GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
  98. /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
  99. GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
  100. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  101. index ebbd76c885..55b55e5b59 100644
  102. --- a/target/riscv/vector_helper.c
  103. +++ b/target/riscv/vector_helper.c
  104. @@ -2502,6 +2502,43 @@ GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2)
  105. GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4)
  106. GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8)
  107. +static inline uint32_t aaddu32(CPURISCVState *env, int vxrm,
  108. + uint32_t a, uint32_t b)
  109. +{
  110. + uint64_t res = (uint64_t)a + b;
  111. + uint8_t round = get_round(vxrm, res, 1);
  112. +
  113. + return (res >> 1) + round;
  114. +}
  115. +
  116. +static inline uint64_t aaddu64(CPURISCVState *env, int vxrm,
  117. + uint64_t a, uint64_t b)
  118. +{
  119. + uint64_t res = a + b;
  120. + uint8_t round = get_round(vxrm, res, 1);
  121. + uint64_t over = (uint64_t)(res < a) << 63;
  122. +
  123. + return ((res >> 1) | over) + round;
  124. +}
  125. +
  126. +RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32)
  127. +RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32)
  128. +RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32)
  129. +RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64)
  130. +GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1)
  131. +GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2)
  132. +GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4)
  133. +GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8)
  134. +
  135. +RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32)
  136. +RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32)
  137. +RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32)
  138. +RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64)
  139. +GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1)
  140. +GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2)
  141. +GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4)
  142. +GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8)
  143. +
  144. static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
  145. {
  146. int64_t res = (int64_t)a - b;
  147. @@ -2538,6 +2575,43 @@ GEN_VEXT_VX_RM(vasub_vx_h, 2, 2)
  148. GEN_VEXT_VX_RM(vasub_vx_w, 4, 4)
  149. GEN_VEXT_VX_RM(vasub_vx_d, 8, 8)
  150. +static inline uint32_t asubu32(CPURISCVState *env, int vxrm,
  151. + uint32_t a, uint32_t b)
  152. +{
  153. + int64_t res = (int64_t)a - b;
  154. + uint8_t round = get_round(vxrm, res, 1);
  155. +
  156. + return (res >> 1) + round;
  157. +}
  158. +
  159. +static inline uint64_t asubu64(CPURISCVState *env, int vxrm,
  160. + uint64_t a, uint64_t b)
  161. +{
  162. + uint64_t res = (uint64_t)a - b;
  163. + uint8_t round = get_round(vxrm, res, 1);
  164. + uint64_t over = (uint64_t)(res > a) << 63;
  165. +
  166. + return ((res >> 1) | over) + round;
  167. +}
  168. +
  169. +RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32)
  170. +RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32)
  171. +RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32)
  172. +RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64)
  173. +GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1)
  174. +GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2)
  175. +GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4)
  176. +GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8)
  177. +
  178. +RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32)
  179. +RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32)
  180. +RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32)
  181. +RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64)
  182. +GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1)
  183. +GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2)
  184. +GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4)
  185. +GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8)
  186. +
  187. /* Vector Single-Width Fractional Multiply with Rounding and Saturation */
  188. static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
  189. {
  190. --
  191. 2.33.1