0047-target-riscv-rvv-1.0-integer-extension-instructions.patch 7.5 KB

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  1. From 0ab96f313a2f424416b0d33bbb148ab1ccc68788 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 17 Aug 2020 13:38:42 +0800
  4. Subject: [PATCH 047/107] target/riscv: rvv-1.0: integer extension instructions
  5. Add the following instructions:
  6. * vzext.vf2
  7. * vzext.vf4
  8. * vzext.vf8
  9. * vsext.vf2
  10. * vsext.vf4
  11. * vsext.vf8
  12. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  13. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  14. ---
  15. target/riscv/helper.h | 14 +++++
  16. target/riscv/insn32.decode | 8 +++
  17. target/riscv/insn_trans/trans_rvv.c.inc | 80 +++++++++++++++++++++++++
  18. target/riscv/vector_helper.c | 31 ++++++++++
  19. 4 files changed, 133 insertions(+)
  20. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  21. index 3e1150d5eb..6d67b67311 100644
  22. --- a/target/riscv/helper.h
  23. +++ b/target/riscv/helper.h
  24. @@ -1147,3 +1147,17 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
  25. DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
  26. DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
  27. DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
  28. +
  29. +DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
  30. +DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
  31. +DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32)
  32. +DEF_HELPER_5(vzext_vf4_w, void, ptr, ptr, ptr, env, i32)
  33. +DEF_HELPER_5(vzext_vf4_d, void, ptr, ptr, ptr, env, i32)
  34. +DEF_HELPER_5(vzext_vf8_d, void, ptr, ptr, ptr, env, i32)
  35. +
  36. +DEF_HELPER_5(vsext_vf2_h, void, ptr, ptr, ptr, env, i32)
  37. +DEF_HELPER_5(vsext_vf2_w, void, ptr, ptr, ptr, env, i32)
  38. +DEF_HELPER_5(vsext_vf2_d, void, ptr, ptr, ptr, env, i32)
  39. +DEF_HELPER_5(vsext_vf4_w, void, ptr, ptr, ptr, env, i32)
  40. +DEF_HELPER_5(vsext_vf4_d, void, ptr, ptr, ptr, env, i32)
  41. +DEF_HELPER_5(vsext_vf8_d, void, ptr, ptr, ptr, env, i32)
  42. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  43. index 230aa74c51..3c735b866d 100644
  44. --- a/target/riscv/insn32.decode
  45. +++ b/target/riscv/insn32.decode
  46. @@ -630,6 +630,14 @@ vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
  47. vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
  48. vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
  49. +# Vector Integer Extension
  50. +vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
  51. +vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
  52. +vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
  53. +vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
  54. +vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
  55. +vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
  56. +
  57. vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
  58. vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
  59. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  60. index d6c68587ab..58f0edc031 100644
  61. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  62. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  63. @@ -3519,3 +3519,83 @@ GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
  64. GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
  65. GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
  66. GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
  67. +
  68. +static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
  69. +{
  70. + uint8_t from = (s->sew + 3) - div;
  71. + bool ret = require_rvv(s) &&
  72. + (from >= 3 && from <= 8) &&
  73. + (a->rd != a->rs2) &&
  74. + require_align(a->rd, s->lmul) &&
  75. + require_align(a->rs2, s->lmul - div) &&
  76. + require_vm(a->vm, a->rd) &&
  77. + require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
  78. + return ret;
  79. +}
  80. +
  81. +static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
  82. +{
  83. + uint32_t data = 0;
  84. + gen_helper_gvec_3_ptr *fn;
  85. + TCGLabel *over = gen_new_label();
  86. + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
  87. +
  88. + static gen_helper_gvec_3_ptr * const fns[6][4] = {
  89. + {
  90. + NULL, gen_helper_vzext_vf2_h,
  91. + gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d
  92. + },
  93. + {
  94. + NULL, NULL,
  95. + gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d,
  96. + },
  97. + {
  98. + NULL, NULL,
  99. + NULL, gen_helper_vzext_vf8_d
  100. + },
  101. + {
  102. + NULL, gen_helper_vsext_vf2_h,
  103. + gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d
  104. + },
  105. + {
  106. + NULL, NULL,
  107. + gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d,
  108. + },
  109. + {
  110. + NULL, NULL,
  111. + NULL, gen_helper_vsext_vf8_d
  112. + }
  113. + };
  114. +
  115. + fn = fns[seq][s->sew];
  116. + if (fn == NULL) {
  117. + return false;
  118. + }
  119. +
  120. + data = FIELD_DP32(data, VDATA, VM, a->vm);
  121. +
  122. + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  123. + vreg_ofs(s, a->rs2), cpu_env, 0,
  124. + s->vlen / 8, data, fn);
  125. +
  126. + mark_vs_dirty(s);
  127. + gen_set_label(over);
  128. + return true;
  129. +}
  130. +
  131. +/* Vector Integer Extension */
  132. +#define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \
  133. +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  134. +{ \
  135. + if (int_ext_check(s, a, DIV)) { \
  136. + return int_ext_op(s, a, SEQ); \
  137. + } \
  138. + return false; \
  139. +}
  140. +
  141. +GEN_INT_EXT_TRANS(vzext_vf2, 1, 0)
  142. +GEN_INT_EXT_TRANS(vzext_vf4, 2, 1)
  143. +GEN_INT_EXT_TRANS(vzext_vf8, 3, 2)
  144. +GEN_INT_EXT_TRANS(vsext_vf2, 1, 3)
  145. +GEN_INT_EXT_TRANS(vsext_vf4, 2, 4)
  146. +GEN_INT_EXT_TRANS(vsext_vf8, 3, 5)
  147. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  148. index 9291f5c9ca..ebbd76c885 100644
  149. --- a/target/riscv/vector_helper.c
  150. +++ b/target/riscv/vector_helper.c
  151. @@ -4750,3 +4750,34 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1)
  152. GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2)
  153. GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
  154. GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
  155. +
  156. +/* Vector Integer Extension */
  157. +#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
  158. +void HELPER(NAME)(void *vd, void *v0, void *vs2, \
  159. + CPURISCVState *env, uint32_t desc) \
  160. +{ \
  161. + uint32_t vl = env->vl; \
  162. + uint32_t vm = vext_vm(desc); \
  163. + uint32_t i; \
  164. + \
  165. + for (i = 0; i < vl; i++) { \
  166. + if (!vm && !vext_elem_mask(v0, i)) { \
  167. + continue; \
  168. + } \
  169. + *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
  170. + } \
  171. +}
  172. +
  173. +GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1)
  174. +GEN_VEXT_INT_EXT(vzext_vf2_w, uint32_t, uint16_t, H4, H2)
  175. +GEN_VEXT_INT_EXT(vzext_vf2_d, uint64_t, uint32_t, H8, H4)
  176. +GEN_VEXT_INT_EXT(vzext_vf4_w, uint32_t, uint8_t, H4, H1)
  177. +GEN_VEXT_INT_EXT(vzext_vf4_d, uint64_t, uint16_t, H8, H2)
  178. +GEN_VEXT_INT_EXT(vzext_vf8_d, uint64_t, uint8_t, H8, H1)
  179. +
  180. +GEN_VEXT_INT_EXT(vsext_vf2_h, int16_t, int8_t, H2, H1)
  181. +GEN_VEXT_INT_EXT(vsext_vf2_w, int32_t, int16_t, H4, H2)
  182. +GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, H4)
  183. +GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1)
  184. +GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2)
  185. +GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1)
  186. --
  187. 2.33.1