0046-target-riscv-rvv-1.0-whole-register-move-instruction.patch 2.8 KB

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  1. From 0c30075fced0c87205d9bec510cade4b421b14b5 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Fri, 14 Aug 2020 17:02:24 +0800
  4. Subject: [PATCH 046/107] target/riscv: rvv-1.0: whole register move
  5. instructions
  6. Add the following instructions:
  7. * vmv1r.v
  8. * vmv2r.v
  9. * vmv4r.v
  10. * vmv8r.v
  11. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  12. ---
  13. target/riscv/insn32.decode | 4 ++++
  14. target/riscv/insn_trans/trans_rvv.c.inc | 25 +++++++++++++++++++++++++
  15. 2 files changed, 29 insertions(+)
  16. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  17. index 41eb9628d3..230aa74c51 100644
  18. --- a/target/riscv/insn32.decode
  19. +++ b/target/riscv/insn32.decode
  20. @@ -625,6 +625,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
  21. vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
  22. vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
  23. vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
  24. +vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
  25. +vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
  26. +vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
  27. +vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
  28. vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
  29. vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
  30. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  31. index 39b5d9a064..d6c68587ab 100644
  32. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  33. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  34. @@ -3494,3 +3494,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
  35. }
  36. return false;
  37. }
  38. +
  39. +/*
  40. + * Whole Vector Register Move Instructions ignore vtype and vl setting.
  41. + * Thus, we don't need to check vill bit. (Section 17.6)
  42. + */
  43. +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
  44. +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
  45. +{ \
  46. + if (require_rvv(s) && \
  47. + QEMU_IS_ALIGNED(a->rd, LEN) && \
  48. + QEMU_IS_ALIGNED(a->rs2, LEN)) { \
  49. + /* EEW = 8 */ \
  50. + tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
  51. + vreg_ofs(s, a->rs2), \
  52. + s->vlen / 8 * LEN, s->vlen / 8 * LEN); \
  53. + mark_vs_dirty(s); \
  54. + return true; \
  55. + } \
  56. + return false; \
  57. +}
  58. +
  59. +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
  60. +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
  61. +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
  62. +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
  63. --
  64. 2.33.1