0045-target-riscv-rvv-1.0-floating-point-scalar-move-inst.patch 4.4 KB

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  1. From f33ffb6ecdc0b978b0980c3117fab6a276f902ff Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Tue, 1 Dec 2020 22:30:18 +0800
  4. Subject: [PATCH 045/107] target/riscv: rvv-1.0: floating-point scalar move
  5. instructions
  6. NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
  7. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  8. ---
  9. target/riscv/insn32.decode | 4 +--
  10. target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++------------
  11. target/riscv/internals.h | 5 ----
  12. 3 files changed, 22 insertions(+), 26 deletions(-)
  13. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  14. index 0b17eed559..41eb9628d3 100644
  15. --- a/target/riscv/insn32.decode
  16. +++ b/target/riscv/insn32.decode
  17. @@ -612,8 +612,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
  18. vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
  19. vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
  20. vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
  21. -vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
  22. -vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
  23. +vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
  24. +vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
  25. vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
  26. vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
  27. vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
  28. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  29. index 0c8b5e232d..39b5d9a064 100644
  30. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  31. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  32. @@ -3282,14 +3282,20 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
  33. /* Floating-Point Scalar Move Instructions */
  34. static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
  35. {
  36. - if (!s->vill && has_ext(s, RVF) &&
  37. - (s->mstatus_fs != 0) && (s->sew != 0)) {
  38. - unsigned int len = 8 << s->sew;
  39. + if (require_rvv(s) &&
  40. + require_rvf(s) &&
  41. + vext_check_isa_ill(s)) {
  42. + unsigned int ofs = (8 << s->sew);
  43. + unsigned int len = 64 - ofs;
  44. + TCGv_i64 t_nan;
  45. vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
  46. - if (len < 64) {
  47. - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
  48. - MAKE_64BIT_MASK(len, 64 - len));
  49. + /* NaN-box f[rd] as necessary for SEW */
  50. + if (len) {
  51. + t_nan = tcg_const_i64(UINT64_MAX);
  52. + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
  53. + t_nan, ofs, len);
  54. + tcg_temp_free_i64(t_nan);
  55. }
  56. mark_fs_dirty(s);
  57. @@ -3301,25 +3307,20 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
  58. /* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
  59. static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
  60. {
  61. - if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
  62. - TCGv_i64 t1;
  63. + if (require_rvv(s) &&
  64. + require_rvf(s) &&
  65. + vext_check_isa_ill(s)) {
  66. /* The instructions ignore LMUL and vector register group. */
  67. - uint32_t vlmax = s->vlen >> 3;
  68. + TCGv_i64 t1;
  69. + TCGLabel *over = gen_new_label();
  70. /* if vl == 0, skip vector register write back */
  71. - TCGLabel *over = gen_new_label();
  72. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
  73. - /* zeroed all elements */
  74. - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
  75. -
  76. - /* NaN-box f[rs1] as necessary for SEW */
  77. + /* NaN-box f[rs1] */
  78. t1 = tcg_temp_new_i64();
  79. - if (s->sew == MO_64 && !has_ext(s, RVD)) {
  80. - tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
  81. - } else {
  82. - tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
  83. - }
  84. + do_nanbox(s, t1, cpu_fpr[a->rs1]);
  85. +
  86. vec_element_storei(s, a->rd, 0, t1);
  87. tcg_temp_free_i64(t1);
  88. mark_vs_dirty(s);
  89. diff --git a/target/riscv/internals.h b/target/riscv/internals.h
  90. index 81f5dfa477..ac062dc0b4 100644
  91. --- a/target/riscv/internals.h
  92. +++ b/target/riscv/internals.h
  93. @@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1);
  94. target_ulong fclass_s(uint64_t frs1);
  95. target_ulong fclass_d(uint64_t frs1);
  96. -#define SEW8 0
  97. -#define SEW16 1
  98. -#define SEW32 2
  99. -#define SEW64 3
  100. -
  101. #ifndef CONFIG_USER_ONLY
  102. extern const VMStateDescription vmstate_riscv_cpu;
  103. #endif
  104. --
  105. 2.33.1