0044-target-riscv-rvv-1.0-floating-point-move-instruction.patch 2.2 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162
  1. From 943f59cdb3255cf6e353565ee1d9360e67f9c5c5 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Tue, 4 Aug 2020 10:27:28 +0800
  4. Subject: [PATCH 044/107] target/riscv: rvv-1.0: floating-point move
  5. instruction
  6. NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
  7. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  8. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  9. ---
  10. target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++++++++++++--
  11. 1 file changed, 14 insertions(+), 2 deletions(-)
  12. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  13. index d83d30c101..0c8b5e232d 100644
  14. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  15. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  16. @@ -2691,9 +2691,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
  17. require_rvf(s) &&
  18. vext_check_isa_ill(s) &&
  19. require_align(a->rd, s->lmul)) {
  20. + TCGv_i64 t1;
  21. +
  22. if (s->vl_eq_vlmax) {
  23. + t1 = tcg_temp_new_i64();
  24. + /* NaN-box f[rs1] */
  25. + do_nanbox(s, t1, cpu_fpr[a->rs1]);
  26. +
  27. tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
  28. - MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
  29. + MAXSZ(s), MAXSZ(s), t1);
  30. mark_vs_dirty(s);
  31. } else {
  32. TCGv_ptr dest;
  33. @@ -2707,16 +2713,22 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
  34. TCGLabel *over = gen_new_label();
  35. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
  36. + t1 = tcg_temp_new_i64();
  37. + /* NaN-box f[rs1] */
  38. + do_nanbox(s, t1, cpu_fpr[a->rs1]);
  39. +
  40. dest = tcg_temp_new_ptr();
  41. desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  42. tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
  43. - fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
  44. +
  45. + fns[s->sew - 1](dest, t1, cpu_env, desc);
  46. tcg_temp_free_ptr(dest);
  47. tcg_temp_free_i32(desc);
  48. mark_vs_dirty(s);
  49. gen_set_label(over);
  50. }
  51. + tcg_temp_free_i64(t1);
  52. return true;
  53. }
  54. return false;
  55. --
  56. 2.33.1