0043-target-riscv-rvv-1.0-integer-scalar-move-instruction.patch 3.5 KB

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  1. From ec37910c0fbfda7dc82b9c032714e3bad3f9ef46 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Tue, 14 Jul 2020 01:16:44 +0800
  4. Subject: [PATCH 043/107] target/riscv: rvv-1.0: integer scalar move
  5. instructions
  6. * Remove "vmv.s.x: dothing if rs1 == 0" constraint.
  7. * Add vmv.x.s instruction.
  8. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  9. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  10. ---
  11. target/riscv/insn32.decode | 3 +-
  12. target/riscv/insn_trans/trans_rvv.c.inc | 45 ++++++++++++++++++++-----
  13. 2 files changed, 39 insertions(+), 9 deletions(-)
  14. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  15. index e1b20b68e7..0b17eed559 100644
  16. --- a/target/riscv/insn32.decode
  17. +++ b/target/riscv/insn32.decode
  18. @@ -609,8 +609,9 @@ vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
  19. vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
  20. viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
  21. vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
  22. +vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
  23. +vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
  24. vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
  25. -vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
  26. vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
  27. vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
  28. vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
  29. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  30. index c517e5302a..d83d30c101 100644
  31. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  32. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  33. @@ -3211,27 +3211,56 @@ static void vec_element_storei(DisasContext *s, int vreg,
  34. store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
  35. }
  36. +/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
  37. +static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
  38. +{
  39. + if (require_rvv(s) &&
  40. + vext_check_isa_ill(s)) {
  41. + TCGv_i64 t1;
  42. + TCGv dest;
  43. +
  44. + t1 = tcg_temp_new_i64();
  45. + dest = tcg_temp_new();
  46. + /*
  47. + * load vreg and sign-extend to 64 bits,
  48. + * then truncate to XLEN bits before storing to gpr.
  49. + */
  50. + vec_element_loadi(s, t1, a->rs2, 0, true);
  51. + tcg_gen_trunc_i64_tl(dest, t1);
  52. + gen_set_gpr(a->rd, dest);
  53. + tcg_temp_free_i64(t1);
  54. + tcg_temp_free(dest);
  55. +
  56. + return true;
  57. + }
  58. + return false;
  59. +}
  60. +
  61. /* vmv.s.x vd, rs1 # vd[0] = rs1 */
  62. static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
  63. {
  64. - if (vext_check_isa_ill(s)) {
  65. + if (require_rvv(s) &&
  66. + vext_check_isa_ill(s)) {
  67. /* This instruction ignores LMUL and vector register groups */
  68. - int maxsz = s->vlen >> 3;
  69. TCGv_i64 t1;
  70. + TCGv s1;
  71. TCGLabel *over = gen_new_label();
  72. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
  73. - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
  74. - if (a->rs1 == 0) {
  75. - goto done;
  76. - }
  77. t1 = tcg_temp_new_i64();
  78. - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
  79. + s1 = tcg_temp_new();
  80. +
  81. + /*
  82. + * load gpr and sign-extend to 64 bits,
  83. + * then truncate to SEW bits when storing to vreg.
  84. + */
  85. + gen_get_gpr(s1, a->rs1);
  86. + tcg_gen_ext_tl_i64(t1, s1);
  87. vec_element_storei(s, a->rd, 0, t1);
  88. tcg_temp_free_i64(t1);
  89. + tcg_temp_free(s1);
  90. mark_vs_dirty(s);
  91. - done:
  92. gen_set_label(over);
  93. return true;
  94. }
  95. --
  96. 2.33.1