0042-target-riscv-rvv-1.0-register-gather-instructions.patch 7.4 KB

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  1. From 76d0e5eb1bf05a113604735c0eb4e25500a7fac2 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 17 Aug 2020 14:25:17 +0800
  4. Subject: [PATCH 042/107] target/riscv: rvv-1.0: register gather instructions
  5. * Add vrgatherei16.vv instruction.
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  8. ---
  9. target/riscv/helper.h | 4 ++++
  10. target/riscv/insn32.decode | 1 +
  11. target/riscv/insn_trans/trans_rvv.c.inc | 27 ++++++++++++++++++++++---
  12. target/riscv/vector_helper.c | 23 ++++++++++++---------
  13. 4 files changed, 43 insertions(+), 12 deletions(-)
  14. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  15. index 8f2d41c610..3e1150d5eb 100644
  16. --- a/target/riscv/helper.h
  17. +++ b/target/riscv/helper.h
  18. @@ -1134,6 +1134,10 @@ DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  19. DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  20. DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  21. DEF_HELPER_6(vrgather_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
  22. +DEF_HELPER_6(vrgatherei16_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
  23. +DEF_HELPER_6(vrgatherei16_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
  24. +DEF_HELPER_6(vrgatherei16_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
  25. +DEF_HELPER_6(vrgatherei16_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
  26. DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32)
  27. DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32)
  28. DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32)
  29. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  30. index 05ccfe9356..e1b20b68e7 100644
  31. --- a/target/riscv/insn32.decode
  32. +++ b/target/riscv/insn32.decode
  33. @@ -620,6 +620,7 @@ vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
  34. vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
  35. vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
  36. vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
  37. +vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
  38. vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
  39. vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
  40. vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
  41. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  42. index a4365e3a19..c517e5302a 100644
  43. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  44. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  45. @@ -3323,7 +3323,25 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
  46. require_vm(a->vm, a->rd);
  47. }
  48. +static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
  49. +{
  50. + int8_t emul = MO_16 - s->sew + s->lmul;
  51. + return require_rvv(s) &&
  52. + vext_check_isa_ill(s) &&
  53. + (emul >= -3 && emul <= 3) &&
  54. + require_align(a->rd, s->lmul) &&
  55. + require_align(a->rs1, emul) &&
  56. + require_align(a->rs2, s->lmul) &&
  57. + (a->rd != a->rs2 && a->rd != a->rs1) &&
  58. + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0),
  59. + a->rs1, 1 << MAX(emul, 0)) &&
  60. + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0),
  61. + a->rs2, 1 << MAX(s->lmul, 0)) &&
  62. + require_vm(a->vm, a->rd);
  63. +}
  64. +
  65. GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
  66. +GEN_OPIVV_TRANS(vrgatherei16_vv, vrgatherei16_vv_check)
  67. static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
  68. {
  69. @@ -3343,7 +3361,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
  70. }
  71. if (a->vm && s->vl_eq_vlmax) {
  72. - int vlmax = s->vlen;
  73. + int scale = s->lmul - (s->sew + 3);
  74. + int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
  75. TCGv_i64 dest = tcg_temp_new_i64();
  76. if (a->rs1 == 0) {
  77. @@ -3374,8 +3393,10 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
  78. }
  79. if (a->vm && s->vl_eq_vlmax) {
  80. - if (a->rs1 >= s->vlen) {
  81. - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
  82. + int scale = s->lmul - (s->sew + 3);
  83. + int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
  84. + if (a->rs1 >= vlmax) {
  85. + tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
  86. MAXSZ(s), MAXSZ(s), 0);
  87. } else {
  88. tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
  89. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  90. index cb12585956..9291f5c9ca 100644
  91. --- a/target/riscv/vector_helper.c
  92. +++ b/target/riscv/vector_helper.c
  93. @@ -4666,11 +4666,11 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
  94. GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
  95. /* Vector Register Gather Instruction */
  96. -#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H) \
  97. +#define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \
  98. void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
  99. CPURISCVState *env, uint32_t desc) \
  100. { \
  101. - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
  102. + uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS1))); \
  103. uint32_t vm = vext_vm(desc); \
  104. uint32_t vl = env->vl; \
  105. uint64_t index; \
  106. @@ -4680,20 +4680,25 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
  107. if (!vm && !vext_elem_mask(v0, i)) { \
  108. continue; \
  109. } \
  110. - index = *((ETYPE *)vs1 + H(i)); \
  111. + index = *((TS1 *)vs1 + HS1(i)); \
  112. if (index >= vlmax) { \
  113. - *((ETYPE *)vd + H(i)) = 0; \
  114. + *((TS2 *)vd + HS2(i)) = 0; \
  115. } else { \
  116. - *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
  117. + *((TS2 *)vd + HS2(i)) = *((TS2 *)vs2 + HS2(index)); \
  118. } \
  119. } \
  120. }
  121. /* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
  122. -GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1)
  123. -GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2)
  124. -GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4)
  125. -GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8)
  126. +GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, uint8_t, H1, H1)
  127. +GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, uint16_t, H2, H2)
  128. +GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, uint32_t, H4, H4)
  129. +GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, uint64_t, H8, H8)
  130. +
  131. +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_b, uint16_t, uint8_t, H2, H1)
  132. +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_h, uint16_t, uint16_t, H2, H2)
  133. +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_w, uint16_t, uint32_t, H2, H4)
  134. +GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_d, uint16_t, uint64_t, H2, H8)
  135. #define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H) \
  136. void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
  137. --
  138. 2.33.1