0041-target-riscv-rvv-1.0-allow-load-element-with-sign-ex.patch 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104
  1. From 03e2b117dd0ead5a60d98120bbb066db4168bd84 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Tue, 21 Jul 2020 00:40:11 +0800
  4. Subject: [PATCH 041/107] target/riscv: rvv-1.0: allow load element with
  5. sign-extended
  6. For some vector instructions (e.g. vmv.s.x), the element is loaded with
  7. sign-extended.
  8. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  9. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  10. ---
  11. target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++--------
  12. 1 file changed, 22 insertions(+), 10 deletions(-)
  13. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  14. index 77f2a8552b..a4365e3a19 100644
  15. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  16. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  17. @@ -3056,17 +3056,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
  18. /* Integer Extract Instruction */
  19. static void load_element(TCGv_i64 dest, TCGv_ptr base,
  20. - int ofs, int sew)
  21. + int ofs, int sew, bool sign)
  22. {
  23. switch (sew) {
  24. case MO_8:
  25. - tcg_gen_ld8u_i64(dest, base, ofs);
  26. + if (!sign) {
  27. + tcg_gen_ld8u_i64(dest, base, ofs);
  28. + } else {
  29. + tcg_gen_ld8s_i64(dest, base, ofs);
  30. + }
  31. break;
  32. case MO_16:
  33. - tcg_gen_ld16u_i64(dest, base, ofs);
  34. + if (!sign) {
  35. + tcg_gen_ld16u_i64(dest, base, ofs);
  36. + } else {
  37. + tcg_gen_ld16s_i64(dest, base, ofs);
  38. + }
  39. break;
  40. case MO_32:
  41. - tcg_gen_ld32u_i64(dest, base, ofs);
  42. + if (!sign) {
  43. + tcg_gen_ld32u_i64(dest, base, ofs);
  44. + } else {
  45. + tcg_gen_ld32s_i64(dest, base, ofs);
  46. + }
  47. break;
  48. case MO_64:
  49. tcg_gen_ld_i64(dest, base, ofs);
  50. @@ -3121,7 +3133,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
  51. /* Perform the load. */
  52. load_element(dest, base,
  53. - vreg_ofs(s, vreg), s->sew);
  54. + vreg_ofs(s, vreg), s->sew, false);
  55. tcg_temp_free_ptr(base);
  56. tcg_temp_free_i32(ofs);
  57. @@ -3139,9 +3151,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
  58. }
  59. static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
  60. - int vreg, int idx)
  61. + int vreg, int idx, bool sign)
  62. {
  63. - load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
  64. + load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
  65. }
  66. static bool trans_vext_x_v(DisasContext *s, arg_r *a)
  67. @@ -3151,7 +3163,7 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
  68. if (a->rs1 == 0) {
  69. /* Special case vmv.x.s rd, vs2. */
  70. - vec_element_loadi(s, tmp, a->rs2, 0);
  71. + vec_element_loadi(s, tmp, a->rs2, 0, false);
  72. } else {
  73. /* This instruction ignores LMUL and vector register groups */
  74. int vlmax = s->vlen >> (3 + s->sew);
  75. @@ -3233,7 +3245,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
  76. (s->mstatus_fs != 0) && (s->sew != 0)) {
  77. unsigned int len = 8 << s->sew;
  78. - vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
  79. + vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
  80. if (len < 64) {
  81. tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
  82. MAKE_64BIT_MASK(len, 64 - len));
  83. @@ -3335,7 +3347,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
  84. TCGv_i64 dest = tcg_temp_new_i64();
  85. if (a->rs1 == 0) {
  86. - vec_element_loadi(s, dest, a->rs2, 0);
  87. + vec_element_loadi(s, dest, a->rs2, 0, false);
  88. } else {
  89. vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
  90. }
  91. --
  92. 2.33.1