0040-target-riscv-rvv-1.0-element-index-instruction.patch 1.2 KB

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  1. From a7826d9b805c2e985ef9705ec4f17a46de00a612 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 2 Jul 2020 11:59:34 +0800
  4. Subject: [PATCH 040/107] target/riscv: rvv-1.0: element index instruction
  5. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  6. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  7. ---
  8. target/riscv/insn32.decode | 2 +-
  9. 1 file changed, 1 insertion(+), 1 deletion(-)
  10. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  11. index fde1aa4088..05ccfe9356 100644
  12. --- a/target/riscv/insn32.decode
  13. +++ b/target/riscv/insn32.decode
  14. @@ -608,7 +608,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
  15. vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
  16. vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
  17. viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
  18. -vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
  19. +vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
  20. vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
  21. vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
  22. vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
  23. --
  24. 2.33.1