0039-target-riscv-rvv-1.0-iota-instruction.patch 2.1 KB

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  1. From 1ba2b152d26eb428c30514fc965ed8f1d2947ea7 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 2 Jul 2020 11:58:38 +0800
  4. Subject: [PATCH 039/107] target/riscv: rvv-1.0: iota instruction
  5. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  6. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  7. ---
  8. target/riscv/insn32.decode | 2 +-
  9. target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++--
  10. 2 files changed, 9 insertions(+), 3 deletions(-)
  11. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  12. index 58ca0a7638..fde1aa4088 100644
  13. --- a/target/riscv/insn32.decode
  14. +++ b/target/riscv/insn32.decode
  15. @@ -607,7 +607,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
  16. vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
  17. vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
  18. vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
  19. -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
  20. +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
  21. vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
  22. vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
  23. vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
  24. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  25. index ae53c83a8d..77f2a8552b 100644
  26. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  27. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  28. @@ -2989,12 +2989,18 @@ GEN_M_TRANS(vmsbf_m)
  29. GEN_M_TRANS(vmsif_m)
  30. GEN_M_TRANS(vmsof_m)
  31. -/* Vector Iota Instruction */
  32. +/*
  33. + * Vector Iota Instruction
  34. + *
  35. + * 1. The destination register cannot overlap the source register.
  36. + * 2. If masked, cannot overlap the mask register ('v0').
  37. + * 3. An illegal instruction exception is raised if vstart is non-zero.
  38. + */
  39. static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
  40. {
  41. if (require_rvv(s) &&
  42. vext_check_isa_ill(s) &&
  43. - require_noover(a->rd, s->lmul, a->rs2, 0) &&
  44. + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
  45. require_vm(a->vm, a->rd) &&
  46. require_align(a->rd, s->lmul)) {
  47. uint32_t data = 0;
  48. --
  49. 2.33.1