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- From 1ba2b152d26eb428c30514fc965ed8f1d2947ea7 Mon Sep 17 00:00:00 2001
- From: Frank Chang <frank.chang@sifive.com>
- Date: Thu, 2 Jul 2020 11:58:38 +0800
- Subject: [PATCH 039/107] target/riscv: rvv-1.0: iota instruction
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- ---
- target/riscv/insn32.decode | 2 +-
- target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++--
- 2 files changed, 9 insertions(+), 3 deletions(-)
- diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
- index 58ca0a7638..fde1aa4088 100644
- --- a/target/riscv/insn32.decode
- +++ b/target/riscv/insn32.decode
- @@ -607,7 +607,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
- vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
- vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
- vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
- -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
- +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
- vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
- vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
- vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
- diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
- index ae53c83a8d..77f2a8552b 100644
- --- a/target/riscv/insn_trans/trans_rvv.c.inc
- +++ b/target/riscv/insn_trans/trans_rvv.c.inc
- @@ -2989,12 +2989,18 @@ GEN_M_TRANS(vmsbf_m)
- GEN_M_TRANS(vmsif_m)
- GEN_M_TRANS(vmsof_m)
-
- -/* Vector Iota Instruction */
- +/*
- + * Vector Iota Instruction
- + *
- + * 1. The destination register cannot overlap the source register.
- + * 2. If masked, cannot overlap the mask register ('v0').
- + * 3. An illegal instruction exception is raised if vstart is non-zero.
- + */
- static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
- {
- if (require_rvv(s) &&
- vext_check_isa_ill(s) &&
- - require_noover(a->rd, s->lmul, a->rs2, 0) &&
- + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
- require_vm(a->vm, a->rd) &&
- require_align(a->rd, s->lmul)) {
- uint32_t data = 0;
- --
- 2.33.1
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