0037-target-riscv-rvv-1.0-find-first-set-mask-bit-instruc.patch 3.4 KB

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  1. From 874cd3e6085af5927a69591edc48734224a7677c Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 2 Jul 2020 11:51:56 +0800
  4. Subject: [PATCH 037/107] target/riscv: rvv-1.0: find-first-set mask bit
  5. instruction
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/helper.h | 2 +-
  10. target/riscv/insn32.decode | 2 +-
  11. target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
  12. target/riscv/vector_helper.c | 6 +++---
  13. 4 files changed, 7 insertions(+), 7 deletions(-)
  14. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  15. index 741f69dc44..8f2d41c610 100644
  16. --- a/target/riscv/helper.h
  17. +++ b/target/riscv/helper.h
  18. @@ -1097,7 +1097,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
  19. DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
  20. -DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
  21. +DEF_HELPER_4(vfirst_m, tl, ptr, ptr, env, i32)
  22. DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32)
  23. DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32)
  24. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  25. index 618ddf963c..c66bc4fad1 100644
  26. --- a/target/riscv/insn32.decode
  27. +++ b/target/riscv/insn32.decode
  28. @@ -603,7 +603,7 @@ vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
  29. vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
  30. vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
  31. vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
  32. -vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
  33. +vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
  34. vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
  35. vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
  36. vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
  37. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  38. index 57ef3ed183..52ad12bf43 100644
  39. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  40. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  41. @@ -2927,7 +2927,7 @@ static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
  42. }
  43. /* vmfirst find-first-set mask bit */
  44. -static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
  45. +static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
  46. {
  47. if (require_rvv(s) &&
  48. vext_check_isa_ill(s)) {
  49. @@ -2946,7 +2946,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
  50. tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
  51. tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
  52. - gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
  53. + gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc);
  54. gen_set_gpr(a->rd, dst);
  55. tcg_temp_free_ptr(mask);
  56. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  57. index cc76b60470..fbde77326e 100644
  58. --- a/target/riscv/vector_helper.c
  59. +++ b/target/riscv/vector_helper.c
  60. @@ -4439,9 +4439,9 @@ target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
  61. return cnt;
  62. }
  63. -/* vmfirst find-first-set mask bit*/
  64. -target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
  65. - uint32_t desc)
  66. +/* vfirst find-first-set mask bit*/
  67. +target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
  68. + uint32_t desc)
  69. {
  70. uint32_t vm = vext_vm(desc);
  71. uint32_t vl = env->vl;
  72. --
  73. 2.33.1