0036-target-riscv-rvv-1.0-mask-population-count-instructi.patch 3.6 KB

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  1. From 0c65425aa1d9040a0f65452ecf80f86f2f0889da Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 2 Jul 2020 11:49:38 +0800
  4. Subject: [PATCH 036/107] target/riscv: rvv-1.0: mask population count
  5. instruction
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/helper.h | 2 +-
  10. target/riscv/insn32.decode | 2 +-
  11. target/riscv/insn_trans/trans_rvv.c.inc | 7 ++++---
  12. target/riscv/vector_helper.c | 6 +++---
  13. 4 files changed, 9 insertions(+), 8 deletions(-)
  14. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  15. index f35cd987ee..741f69dc44 100644
  16. --- a/target/riscv/helper.h
  17. +++ b/target/riscv/helper.h
  18. @@ -1095,7 +1095,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
  19. DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
  20. DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
  21. -DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
  22. +DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
  23. DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
  24. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  25. index ac04311bca..618ddf963c 100644
  26. --- a/target/riscv/insn32.decode
  27. +++ b/target/riscv/insn32.decode
  28. @@ -602,7 +602,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
  29. vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
  30. vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
  31. vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
  32. -vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm
  33. +vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
  34. vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
  35. vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
  36. vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
  37. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  38. index 71f2343d4d..57ef3ed183 100644
  39. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  40. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  41. @@ -2893,8 +2893,8 @@ GEN_MM_TRANS(vmnor_mm)
  42. GEN_MM_TRANS(vmornot_mm)
  43. GEN_MM_TRANS(vmxnor_mm)
  44. -/* Vector mask population count vmpopc */
  45. -static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
  46. +/* Vector mask population count vpopc */
  47. +static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
  48. {
  49. if (require_rvv(s) &&
  50. vext_check_isa_ill(s)) {
  51. @@ -2913,13 +2913,14 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
  52. tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
  53. tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
  54. - gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
  55. + gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc);
  56. gen_set_gpr(a->rd, dst);
  57. tcg_temp_free_ptr(mask);
  58. tcg_temp_free_ptr(src2);
  59. tcg_temp_free(dst);
  60. tcg_temp_free_i32(desc);
  61. +
  62. return true;
  63. }
  64. return false;
  65. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  66. index 0a9fb898a1..cc76b60470 100644
  67. --- a/target/riscv/vector_helper.c
  68. +++ b/target/riscv/vector_helper.c
  69. @@ -4420,9 +4420,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
  70. GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
  71. GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)
  72. -/* Vector mask population count vmpopc */
  73. -target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
  74. - uint32_t desc)
  75. +/* Vector mask population count vpopc */
  76. +target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
  77. + uint32_t desc)
  78. {
  79. target_ulong cnt = 0;
  80. uint32_t vm = vext_vm(desc);
  81. --
  82. 2.33.1