0031-target-riscv-rvv-1.0-load-store-whole-register-instr.patch 9.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244
  1. From fd907cac2c360bd2442ffd809212e0c7428b41e5 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 17 Aug 2020 09:41:07 +0800
  4. Subject: [PATCH 031/107] target/riscv: rvv-1.0: load/store whole register
  5. instructions
  6. Add the following instructions:
  7. * vl<nf>re<eew>.v
  8. * vs<nf>r.v
  9. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  10. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  11. ---
  12. target/riscv/helper.h | 21 ++++++++
  13. target/riscv/insn32.decode | 22 ++++++++
  14. target/riscv/insn_trans/trans_rvv.c.inc | 69 +++++++++++++++++++++++++
  15. target/riscv/vector_helper.c | 65 +++++++++++++++++++++++
  16. 4 files changed, 177 insertions(+)
  17. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  18. index f26af64d5b..f35cd987ee 100644
  19. --- a/target/riscv/helper.h
  20. +++ b/target/riscv/helper.h
  21. @@ -174,6 +174,27 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
  22. DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
  23. DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
  24. +DEF_HELPER_4(vl1re8_v, void, ptr, tl, env, i32)
  25. +DEF_HELPER_4(vl1re16_v, void, ptr, tl, env, i32)
  26. +DEF_HELPER_4(vl1re32_v, void, ptr, tl, env, i32)
  27. +DEF_HELPER_4(vl1re64_v, void, ptr, tl, env, i32)
  28. +DEF_HELPER_4(vl2re8_v, void, ptr, tl, env, i32)
  29. +DEF_HELPER_4(vl2re16_v, void, ptr, tl, env, i32)
  30. +DEF_HELPER_4(vl2re32_v, void, ptr, tl, env, i32)
  31. +DEF_HELPER_4(vl2re64_v, void, ptr, tl, env, i32)
  32. +DEF_HELPER_4(vl4re8_v, void, ptr, tl, env, i32)
  33. +DEF_HELPER_4(vl4re16_v, void, ptr, tl, env, i32)
  34. +DEF_HELPER_4(vl4re32_v, void, ptr, tl, env, i32)
  35. +DEF_HELPER_4(vl4re64_v, void, ptr, tl, env, i32)
  36. +DEF_HELPER_4(vl8re8_v, void, ptr, tl, env, i32)
  37. +DEF_HELPER_4(vl8re16_v, void, ptr, tl, env, i32)
  38. +DEF_HELPER_4(vl8re32_v, void, ptr, tl, env, i32)
  39. +DEF_HELPER_4(vl8re64_v, void, ptr, tl, env, i32)
  40. +DEF_HELPER_4(vs1r_v, void, ptr, tl, env, i32)
  41. +DEF_HELPER_4(vs2r_v, void, ptr, tl, env, i32)
  42. +DEF_HELPER_4(vs4r_v, void, ptr, tl, env, i32)
  43. +DEF_HELPER_4(vs8r_v, void, ptr, tl, env, i32)
  44. +
  45. DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
  46. DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
  47. DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
  48. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  49. index ae406dff3b..dec3fe1f34 100644
  50. --- a/target/riscv/insn32.decode
  51. +++ b/target/riscv/insn32.decode
  52. @@ -278,6 +278,28 @@ vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
  53. vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
  54. vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
  55. +# Vector whole register insns
  56. +vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
  57. +vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2
  58. +vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2
  59. +vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2
  60. +vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2
  61. +vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2
  62. +vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2
  63. +vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2
  64. +vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2
  65. +vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2
  66. +vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2
  67. +vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2
  68. +vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2
  69. +vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2
  70. +vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2
  71. +vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2
  72. +vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
  73. +vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2
  74. +vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2
  75. +vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2
  76. +
  77. #*** Vector AMO operations are encoded under the standard AMO major opcode ***
  78. vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm
  79. vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm
  80. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  81. index 5057dff5eb..146d330894 100644
  82. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  83. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  84. @@ -1014,6 +1014,75 @@ GEN_VEXT_TRANS(vle16ff_v, MO_16, r2nfvm, ldff_op, ld_us_check)
  85. GEN_VEXT_TRANS(vle32ff_v, MO_32, r2nfvm, ldff_op, ld_us_check)
  86. GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
  87. +/*
  88. + * load and store whole register instructions
  89. + */
  90. +typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
  91. +
  92. +static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
  93. + gen_helper_ldst_whole *fn, DisasContext *s,
  94. + bool is_store)
  95. +{
  96. + TCGv_ptr dest;
  97. + TCGv base;
  98. + TCGv_i32 desc;
  99. +
  100. + uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
  101. + dest = tcg_temp_new_ptr();
  102. + base = tcg_temp_new();
  103. + desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
  104. +
  105. + gen_get_gpr(base, rs1);
  106. + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
  107. +
  108. + fn(dest, base, cpu_env, desc);
  109. +
  110. + tcg_temp_free_ptr(dest);
  111. + tcg_temp_free(base);
  112. + tcg_temp_free_i32(desc);
  113. + if (!is_store) {
  114. + mark_vs_dirty(s);
  115. + }
  116. + return true;
  117. +}
  118. +
  119. +/*
  120. + * load and store whole register instructions ignore vtype and vl setting.
  121. + * Thus, we don't need to check vill bit. (Section 7.9)
  122. + */
  123. +#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE) \
  124. +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
  125. +{ \
  126. + if (require_rvv(s) && \
  127. + QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
  128. + return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \
  129. + s, IS_STORE); \
  130. + } \
  131. + return false; \
  132. +}
  133. +
  134. +GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, false)
  135. +GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false)
  136. +GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false)
  137. +GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false)
  138. +GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, false)
  139. +GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false)
  140. +GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false)
  141. +GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false)
  142. +GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, false)
  143. +GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false)
  144. +GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false)
  145. +GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false)
  146. +GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, false)
  147. +GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false)
  148. +GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false)
  149. +GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false)
  150. +
  151. +GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true)
  152. +GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true)
  153. +GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true)
  154. +GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
  155. +
  156. /*
  157. *** vector atomic operation
  158. */
  159. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  160. index 8bc3bf77a3..05ec6e040c 100644
  161. --- a/target/riscv/vector_helper.c
  162. +++ b/target/riscv/vector_helper.c
  163. @@ -534,6 +534,71 @@ GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h)
  164. GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w)
  165. GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
  166. +/*
  167. + *** load and store whole register instructions
  168. + */
  169. +static void
  170. +vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
  171. + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
  172. + MMUAccessType access_type)
  173. +{
  174. + uint32_t i, k;
  175. + uint32_t nf = vext_nf(desc);
  176. + uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
  177. + uint32_t max_elems = vlenb >> esz;
  178. +
  179. + /* probe every access */
  180. + probe_pages(env, base, vlenb * nf, ra, access_type);
  181. +
  182. + /* load bytes from guest memory */
  183. + for (k = 0; k < nf; k++) {
  184. + for (i = 0; i < max_elems; i++) {
  185. + target_ulong addr = base + ((i + k * max_elems) << esz);
  186. + ldst_elem(env, addr, i + k * max_elems, vd, ra);
  187. + }
  188. + }
  189. +}
  190. +
  191. +#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \
  192. +void HELPER(NAME)(void *vd, target_ulong base, \
  193. + CPURISCVState *env, uint32_t desc) \
  194. +{ \
  195. + vext_ldst_whole(vd, base, env, desc, LOAD_FN, \
  196. + ctzl(sizeof(ETYPE)), GETPC(), \
  197. + MMU_DATA_LOAD); \
  198. +}
  199. +
  200. +GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b)
  201. +GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h)
  202. +GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w)
  203. +GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d)
  204. +GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b)
  205. +GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h)
  206. +GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w)
  207. +GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d)
  208. +GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b)
  209. +GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h)
  210. +GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w)
  211. +GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d)
  212. +GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b)
  213. +GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h)
  214. +GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w)
  215. +GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d)
  216. +
  217. +#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \
  218. +void HELPER(NAME)(void *vd, target_ulong base, \
  219. + CPURISCVState *env, uint32_t desc) \
  220. +{ \
  221. + vext_ldst_whole(vd, base, env, desc, STORE_FN, \
  222. + ctzl(sizeof(ETYPE)), GETPC(), \
  223. + MMU_DATA_STORE); \
  224. +}
  225. +
  226. +GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b)
  227. +GEN_VEXT_ST_WHOLE(vs2r_v, int8_t, ste_b)
  228. +GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b)
  229. +GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
  230. +
  231. /*
  232. *** Vector AMO Operations (Zvamo)
  233. */
  234. --
  235. 2.33.1