0029-target-riscv-rvv-1.0-fault-only-first-unit-stride-lo.patch 11 KB

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  1. From 05823ddce2559fb9cb01fd318a619c67f05f7295 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Wed, 8 Jul 2020 11:49:28 +0800
  4. Subject: [PATCH 029/107] target/riscv: rvv-1.0: fault-only-first unit stride
  5. load
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  9. ---
  10. target/riscv/helper.h | 27 +++---------
  11. target/riscv/insn32.decode | 14 +++----
  12. target/riscv/insn_trans/trans_rvv.c.inc | 33 ++++-----------
  13. target/riscv/vector_helper.c | 56 +++++++++----------------
  14. 4 files changed, 39 insertions(+), 91 deletions(-)
  15. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  16. index 927d28d53a..bbea5403fb 100644
  17. --- a/target/riscv/helper.h
  18. +++ b/target/riscv/helper.h
  19. @@ -169,28 +169,11 @@ DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
  20. DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
  21. DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
  22. DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
  23. -DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
  24. -DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
  25. -DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
  26. -DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32)
  27. -DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32)
  28. -DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32)
  29. -DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32)
  30. -DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32)
  31. -DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32)
  32. -DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32)
  33. -DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32)
  34. -DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32)
  35. -DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32)
  36. -DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32)
  37. -DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32)
  38. -DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32)
  39. -DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32)
  40. -DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32)
  41. -DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
  42. -DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
  43. -DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
  44. -DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
  45. +DEF_HELPER_5(vle8ff_v, void, ptr, ptr, tl, env, i32)
  46. +DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
  47. +DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
  48. +DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
  49. +
  50. #ifdef TARGET_RISCV64
  51. DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
  52. DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
  53. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  54. index 05c3c18028..97b9b8f5f5 100644
  55. --- a/target/riscv/insn32.decode
  56. +++ b/target/riscv/insn32.decode
  57. @@ -260,14 +260,6 @@ vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
  58. vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
  59. vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
  60. -vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
  61. -vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
  62. -vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
  63. -vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
  64. -vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
  65. -vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
  66. -vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
  67. -
  68. # Vector ordered-indexed and unordered-indexed load insns.
  69. vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
  70. vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
  71. @@ -280,6 +272,12 @@ vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
  72. vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
  73. vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
  74. +# Vector unit-stride fault-only-first load insns.
  75. +vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
  76. +vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
  77. +vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
  78. +vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
  79. +
  80. #*** Vector AMO operations are encoded under the standard AMO major opcode ***
  81. vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
  82. vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
  83. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  84. index 74dd7ee387..14974ce288 100644
  85. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  86. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  87. @@ -943,28 +943,16 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
  88. return true;
  89. }
  90. -static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
  91. +static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
  92. {
  93. uint32_t data = 0;
  94. gen_helper_ldst_us *fn;
  95. - static gen_helper_ldst_us * const fns[7][4] = {
  96. - { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
  97. - gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
  98. - { NULL, gen_helper_vlhff_v_h,
  99. - gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
  100. - { NULL, NULL,
  101. - gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
  102. - { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
  103. - gen_helper_vleff_v_w, gen_helper_vleff_v_d },
  104. - { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
  105. - gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
  106. - { NULL, gen_helper_vlhuff_v_h,
  107. - gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
  108. - { NULL, NULL,
  109. - gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
  110. + static gen_helper_ldst_us * const fns[4] = {
  111. + gen_helper_vle8ff_v, gen_helper_vle16ff_v,
  112. + gen_helper_vle32ff_v, gen_helper_vle64ff_v
  113. };
  114. - fn = fns[seq][s->sew];
  115. + fn = fns[eew];
  116. if (fn == NULL) {
  117. return false;
  118. }
  119. @@ -975,13 +963,10 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
  120. return ldff_trans(a->rd, a->rs1, data, fn, s);
  121. }
  122. -GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
  123. -GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
  124. -GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
  125. -GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
  126. -GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
  127. -GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
  128. -GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
  129. +GEN_VEXT_TRANS(vle8ff_v, MO_8, r2nfvm, ldff_op, ld_us_check)
  130. +GEN_VEXT_TRANS(vle16ff_v, MO_16, r2nfvm, ldff_op, ld_us_check)
  131. +GEN_VEXT_TRANS(vle32ff_v, MO_32, r2nfvm, ldff_op, ld_us_check)
  132. +GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
  133. /*
  134. *** vector atomic operation
  135. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  136. index 6030fa6fbb..affe024600 100644
  137. --- a/target/riscv/vector_helper.c
  138. +++ b/target/riscv/vector_helper.c
  139. @@ -458,7 +458,7 @@ static inline void
  140. vext_ldff(void *vd, void *v0, target_ulong base,
  141. CPURISCVState *env, uint32_t desc,
  142. vext_ldst_elem_fn *ldst_elem,
  143. - uint32_t esz, uint32_t msz, uintptr_t ra)
  144. + uint32_t esz, uintptr_t ra)
  145. {
  146. void *host;
  147. uint32_t i, k, vl = 0;
  148. @@ -472,24 +472,24 @@ vext_ldff(void *vd, void *v0, target_ulong base,
  149. if (!vm && !vext_elem_mask(v0, i)) {
  150. continue;
  151. }
  152. - addr = base + nf * i * msz;
  153. + addr = base + nf * i * esz;
  154. if (i == 0) {
  155. - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
  156. + probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
  157. } else {
  158. /* if it triggers an exception, no need to check watchpoint */
  159. - remain = nf * msz;
  160. + remain = nf * esz;
  161. while (remain > 0) {
  162. offset = -(addr | TARGET_PAGE_MASK);
  163. host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
  164. cpu_mmu_index(env, false));
  165. if (host) {
  166. #ifdef CONFIG_USER_ONLY
  167. - if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
  168. + if (page_check_range(addr, nf * esz, PAGE_READ) < 0) {
  169. vl = i;
  170. goto ProbeSuccess;
  171. }
  172. #else
  173. - probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
  174. + probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
  175. #endif
  176. } else {
  177. vl = i;
  178. @@ -514,43 +514,25 @@ ProbeSuccess:
  179. continue;
  180. }
  181. while (k < nf) {
  182. - target_ulong addr = base + (i * nf + k) * msz;
  183. + target_ulong addr = base + (i * nf + k) * esz;
  184. ldst_elem(env, addr, i + k * vlmax, vd, ra);
  185. k++;
  186. }
  187. }
  188. }
  189. -#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN) \
  190. -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
  191. - CPURISCVState *env, uint32_t desc) \
  192. -{ \
  193. - vext_ldff(vd, v0, base, env, desc, LOAD_FN, \
  194. - sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
  195. -}
  196. -
  197. -GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b)
  198. -GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h)
  199. -GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w)
  200. -GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d)
  201. -GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h)
  202. -GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w)
  203. -GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d)
  204. -GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w)
  205. -GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d)
  206. -GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b)
  207. -GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h)
  208. -GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w)
  209. -GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d)
  210. -GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b)
  211. -GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h)
  212. -GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w)
  213. -GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d)
  214. -GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h)
  215. -GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w)
  216. -GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d)
  217. -GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w)
  218. -GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d)
  219. +#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \
  220. +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
  221. + CPURISCVState *env, uint32_t desc) \
  222. +{ \
  223. + vext_ldff(vd, v0, base, env, desc, LOAD_FN, \
  224. + sizeof(ETYPE), GETPC()); \
  225. +}
  226. +
  227. +GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b)
  228. +GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h)
  229. +GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w)
  230. +GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
  231. /*
  232. *** Vector AMO Operations (Zvamo)
  233. --
  234. 2.33.1