0028-target-riscv-rvv-1.0-fix-address-index-overflow-bug-.patch 1.4 KB

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  1. From e5371e625fb79eab06d70b03ca410102f56fd7ca Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 9 Jul 2020 21:25:17 +0800
  4. Subject: [PATCH 028/107] target/riscv: rvv-1.0: fix address index overflow bug
  5. of indexed load/store insns
  6. Replace ETYPE from signed int to unsigned int to prevent index overflow
  7. issue, which would lead to wrong index address.
  8. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  9. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  10. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  11. ---
  12. target/riscv/vector_helper.c | 8 ++++----
  13. 1 file changed, 4 insertions(+), 4 deletions(-)
  14. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
  15. index 95d367489b..6030fa6fbb 100644
  16. --- a/target/riscv/vector_helper.c
  17. +++ b/target/riscv/vector_helper.c
  18. @@ -361,10 +361,10 @@ static target_ulong NAME(target_ulong base, \
  19. return (base + *((ETYPE *)vs2 + H(idx))); \
  20. }
  21. -GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
  22. -GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
  23. -GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
  24. -GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
  25. +GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
  26. +GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
  27. +GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
  28. +GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
  29. static inline void
  30. vext_ldst_index(void *vd, void *v0, target_ulong base,
  31. --
  32. 2.33.1