0024-target-riscv-rvv-1.0-add-translation-time-nan-box-he.patch 2.8 KB

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  1. From d05effb256790ae2f68ed1bd9fe769bd4108fac5 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Wed, 5 Aug 2020 11:36:39 +0800
  4. Subject: [PATCH 024/107] target/riscv: rvv:1.0: add translation-time nan-box
  5. helper function
  6. * Add fp16 nan-box check generator function, if a 16-bit input is not
  7. properly nanboxed, then the input is replaced with the default qnan.
  8. * Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
  9. generate the NaN-boxed floating-point values based on SEW setting.
  10. * Apply nanbox helper in opfvf_trans().
  11. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  12. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  13. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  14. ---
  15. target/riscv/insn_trans/trans_rvv.c.inc | 35 ++++++++++++++++++++++++-
  16. 1 file changed, 34 insertions(+), 1 deletion(-)
  17. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  18. index 99d14caa14..dcffc14909 100644
  19. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  20. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  21. @@ -2100,6 +2100,33 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx)
  22. /*
  23. *** Vector Float Point Arithmetic Instructions
  24. */
  25. +
  26. +/*
  27. + * As RVF-only cpus always have values NaN-boxed to 64-bits,
  28. + * RVF and RVD can be treated equally.
  29. + * We don't have to deal with the cases of: SEW > FLEN.
  30. + *
  31. + * If SEW < FLEN, check whether input fp register is a valid
  32. + * NaN-boxed value, in which case the least-significant SEW bits
  33. + * of the f regsiter are used, else the canonical NaN value is used.
  34. + */
  35. +static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
  36. +{
  37. + switch (s->sew) {
  38. + case 1:
  39. + gen_check_nanbox_h(out, in);
  40. + break;
  41. + case 2:
  42. + gen_check_nanbox_s(out, in);
  43. + break;
  44. + case 3:
  45. + tcg_gen_mov_i64(out, in);
  46. + break;
  47. + default:
  48. + g_assert_not_reached();
  49. + }
  50. +}
  51. +
  52. /* Vector Single-Width Floating-Point Add/Subtract Instructions */
  53. /*
  54. @@ -2152,6 +2179,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  55. {
  56. TCGv_ptr dest, src2, mask;
  57. TCGv_i32 desc;
  58. + TCGv_i64 t1;
  59. TCGLabel *over = gen_new_label();
  60. tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
  61. @@ -2165,12 +2193,17 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  62. tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
  63. tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
  64. - fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
  65. + /* NaN-box f[rs1] */
  66. + t1 = tcg_temp_new_i64();
  67. + do_nanbox(s, t1, cpu_fpr[rs1]);
  68. +
  69. + fn(dest, mask, t1, src2, cpu_env, desc);
  70. tcg_temp_free_ptr(dest);
  71. tcg_temp_free_ptr(mask);
  72. tcg_temp_free_ptr(src2);
  73. tcg_temp_free_i32(desc);
  74. + tcg_temp_free_i64(t1);
  75. mark_vs_dirty(s);
  76. gen_set_label(over);
  77. return true;
  78. --
  79. 2.33.1