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- From 4220f76f5873fa15198fae534c29d5b40f2aed76 Mon Sep 17 00:00:00 2001
- From: LIU Zhiwei <zhiwei_liu@c-sky.com>
- Date: Thu, 16 Jul 2020 02:06:51 +0800
- Subject: [PATCH 016/107] target/riscv: rvv-1.0: add vcsr register
- Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
- Signed-off-by: Frank Chang <frank.chang@sifive.com>
- Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
- Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
- ---
- target/riscv/cpu_bits.h | 7 +++++++
- target/riscv/csr.c | 21 +++++++++++++++++++++
- 2 files changed, 28 insertions(+)
- diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
- index 2073abfabf..9ad27ff280 100644
- --- a/target/riscv/cpu_bits.h
- +++ b/target/riscv/cpu_bits.h
- @@ -60,9 +60,16 @@
- #define CSR_VSTART 0x008
- #define CSR_VXSAT 0x009
- #define CSR_VXRM 0x00a
- +#define CSR_VCSR 0x00f
- #define CSR_VL 0xc20
- #define CSR_VTYPE 0xc21
-
- +/* VCSR fields */
- +#define VCSR_VXSAT_SHIFT 0
- +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
- +#define VCSR_VXRM_SHIFT 1
- +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
- +
- /* User Timers and Counters */
- #define CSR_CYCLE 0xc00
- #define CSR_TIME 0xc01
- diff --git a/target/riscv/csr.c b/target/riscv/csr.c
- index 7992bdc07e..6e19677318 100644
- --- a/target/riscv/csr.c
- +++ b/target/riscv/csr.c
- @@ -327,6 +327,26 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
- return 0;
- }
-
- +static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
- +{
- + *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
- + return 0;
- +}
- +
- +static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
- +{
- +#if !defined(CONFIG_USER_ONLY)
- + if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
- + return -RISCV_EXCP_ILLEGAL_INST;
- + }
- + env->mstatus |= MSTATUS_VS;
- +#endif
- +
- + env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
- + env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
- + return 0;
- +}
- +
- /* User Timers and Counters */
- static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
- {
- @@ -1390,6 +1410,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
- [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
- [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
- [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
- + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
- [CSR_VL] = { "vl", vs, read_vl },
- [CSR_VTYPE] = { "vtype", vs, read_vtype },
- /* User Timers and Counters */
- --
- 2.33.1
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