0016-target-riscv-rvv-1.0-add-vcsr-register.patch 2.7 KB

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  1. From 4220f76f5873fa15198fae534c29d5b40f2aed76 Mon Sep 17 00:00:00 2001
  2. From: LIU Zhiwei <zhiwei_liu@c-sky.com>
  3. Date: Thu, 16 Jul 2020 02:06:51 +0800
  4. Subject: [PATCH 016/107] target/riscv: rvv-1.0: add vcsr register
  5. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  9. ---
  10. target/riscv/cpu_bits.h | 7 +++++++
  11. target/riscv/csr.c | 21 +++++++++++++++++++++
  12. 2 files changed, 28 insertions(+)
  13. diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
  14. index 2073abfabf..9ad27ff280 100644
  15. --- a/target/riscv/cpu_bits.h
  16. +++ b/target/riscv/cpu_bits.h
  17. @@ -60,9 +60,16 @@
  18. #define CSR_VSTART 0x008
  19. #define CSR_VXSAT 0x009
  20. #define CSR_VXRM 0x00a
  21. +#define CSR_VCSR 0x00f
  22. #define CSR_VL 0xc20
  23. #define CSR_VTYPE 0xc21
  24. +/* VCSR fields */
  25. +#define VCSR_VXSAT_SHIFT 0
  26. +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
  27. +#define VCSR_VXRM_SHIFT 1
  28. +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
  29. +
  30. /* User Timers and Counters */
  31. #define CSR_CYCLE 0xc00
  32. #define CSR_TIME 0xc01
  33. diff --git a/target/riscv/csr.c b/target/riscv/csr.c
  34. index 7992bdc07e..6e19677318 100644
  35. --- a/target/riscv/csr.c
  36. +++ b/target/riscv/csr.c
  37. @@ -327,6 +327,26 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
  38. return 0;
  39. }
  40. +static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
  41. +{
  42. + *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
  43. + return 0;
  44. +}
  45. +
  46. +static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
  47. +{
  48. +#if !defined(CONFIG_USER_ONLY)
  49. + if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
  50. + return -RISCV_EXCP_ILLEGAL_INST;
  51. + }
  52. + env->mstatus |= MSTATUS_VS;
  53. +#endif
  54. +
  55. + env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
  56. + env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
  57. + return 0;
  58. +}
  59. +
  60. /* User Timers and Counters */
  61. static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
  62. {
  63. @@ -1390,6 +1410,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
  64. [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
  65. [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
  66. [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
  67. + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
  68. [CSR_VL] = { "vl", vs, read_vl },
  69. [CSR_VTYPE] = { "vtype", vs, read_vtype },
  70. /* User Timers and Counters */
  71. --
  72. 2.33.1