0015-target-riscv-rvv-1.0-remove-rvv-related-codes-from-f.patch 2.0 KB

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  1. From 4e5d37969dbab98adb2f537cf0bb5cbb97c4e98e Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Fri, 7 Aug 2020 14:53:53 +0800
  4. Subject: [PATCH 015/107] target/riscv: rvv-1.0: remove rvv related codes from
  5. fcsr registers
  6. * Remove VXRM and VXSAT fields from FCSR register as they are only
  7. presented in VCSR register.
  8. * Remove RVV loose check in fs() predicate function.
  9. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  10. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  11. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  12. ---
  13. target/riscv/csr.c | 13 -------------
  14. 1 file changed, 13 deletions(-)
  15. diff --git a/target/riscv/csr.c b/target/riscv/csr.c
  16. index 3a77d2cb86..7992bdc07e 100644
  17. --- a/target/riscv/csr.c
  18. +++ b/target/riscv/csr.c
  19. @@ -38,10 +38,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
  20. static int fs(CPURISCVState *env, int csrno)
  21. {
  22. #if !defined(CONFIG_USER_ONLY)
  23. - /* loose check condition for fcsr in vector extension */
  24. - if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
  25. - return 0;
  26. - }
  27. if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  28. return -RISCV_EXCP_ILLEGAL_INST;
  29. }
  30. @@ -246,10 +242,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
  31. #endif
  32. *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
  33. | (env->frm << FSR_RD_SHIFT);
  34. - if (vs(env, csrno) >= 0) {
  35. - *val |= (env->vxrm << FSR_VXRM_SHIFT)
  36. - | (env->vxsat << FSR_VXSAT_SHIFT);
  37. - }
  38. return 0;
  39. }
  40. @@ -260,13 +252,8 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
  41. return -RISCV_EXCP_ILLEGAL_INST;
  42. }
  43. env->mstatus |= MSTATUS_FS;
  44. - env->mstatus |= MSTATUS_VS;
  45. #endif
  46. env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
  47. - if (vs(env, csrno) >= 0) {
  48. - env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
  49. - env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
  50. - }
  51. riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
  52. return 0;
  53. }
  54. --
  55. 2.33.1