0014-target-riscv-rvv-1.0-add-translation-time-vector-con.patch 21 KB

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  1. From d2115a910cd95567bbd0526d7c5766e35d14c4bf Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 5 Oct 2020 15:21:15 +0800
  4. Subject: [PATCH 014/107] target/riscv: rvv-1.0: add translation-time vector
  5. context status
  6. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
  7. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  8. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  9. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  10. ---
  11. target/riscv/insn_trans/trans_rvv.c.inc | 69 ++++++++++++++++++++-----
  12. target/riscv/translate.c | 33 ++++++++++++
  13. 2 files changed, 90 insertions(+), 12 deletions(-)
  14. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  15. index 887c6b8883..56ce39e769 100644
  16. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  17. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  18. @@ -41,6 +41,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
  19. gen_get_gpr(s2, a->rs2);
  20. gen_helper_vsetvl(dst, cpu_env, s1, s2);
  21. gen_set_gpr(a->rd, dst);
  22. + mark_vs_dirty(ctx);
  23. tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
  24. lookup_and_goto_ptr(ctx);
  25. ctx->base.is_jmp = DISAS_NORETURN;
  26. @@ -72,6 +73,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
  27. }
  28. gen_helper_vsetvl(dst, cpu_env, s1, s2);
  29. gen_set_gpr(a->rd, dst);
  30. + mark_vs_dirty(ctx);
  31. gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
  32. ctx->base.is_jmp = DISAS_NORETURN;
  33. @@ -163,7 +165,8 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
  34. TCGv_env, TCGv_i32);
  35. static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
  36. - gen_helper_ldst_us *fn, DisasContext *s)
  37. + gen_helper_ldst_us *fn, DisasContext *s,
  38. + bool is_store)
  39. {
  40. TCGv_ptr dest, mask;
  41. TCGv base;
  42. @@ -195,6 +198,9 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
  43. tcg_temp_free_ptr(mask);
  44. tcg_temp_free(base);
  45. tcg_temp_free_i32(desc);
  46. + if (!is_store) {
  47. + mark_vs_dirty(s);
  48. + }
  49. gen_set_label(over);
  50. return true;
  51. }
  52. @@ -245,7 +251,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
  53. data = FIELD_DP32(data, VDATA, VM, a->vm);
  54. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  55. data = FIELD_DP32(data, VDATA, NF, a->nf);
  56. - return ldst_us_trans(a->rd, a->rs1, data, fn, s);
  57. + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
  58. }
  59. static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
  60. @@ -298,7 +304,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
  61. data = FIELD_DP32(data, VDATA, VM, a->vm);
  62. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  63. data = FIELD_DP32(data, VDATA, NF, a->nf);
  64. - return ldst_us_trans(a->rd, a->rs1, data, fn, s);
  65. + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
  66. }
  67. static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
  68. @@ -321,7 +327,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
  69. static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
  70. uint32_t data, gen_helper_ldst_stride *fn,
  71. - DisasContext *s)
  72. + DisasContext *s, bool is_store)
  73. {
  74. TCGv_ptr dest, mask;
  75. TCGv base, stride;
  76. @@ -348,6 +354,9 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
  77. tcg_temp_free(base);
  78. tcg_temp_free(stride);
  79. tcg_temp_free_i32(desc);
  80. + if (!is_store) {
  81. + mark_vs_dirty(s);
  82. + }
  83. gen_set_label(over);
  84. return true;
  85. }
  86. @@ -382,7 +391,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
  87. data = FIELD_DP32(data, VDATA, VM, a->vm);
  88. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  89. data = FIELD_DP32(data, VDATA, NF, a->nf);
  90. - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
  91. + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
  92. }
  93. static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
  94. @@ -426,7 +435,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
  95. return false;
  96. }
  97. - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
  98. + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
  99. }
  100. static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
  101. @@ -449,7 +458,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
  102. static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  103. uint32_t data, gen_helper_ldst_index *fn,
  104. - DisasContext *s)
  105. + DisasContext *s, bool is_store)
  106. {
  107. TCGv_ptr dest, mask, index;
  108. TCGv base;
  109. @@ -476,6 +485,9 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  110. tcg_temp_free_ptr(index);
  111. tcg_temp_free(base);
  112. tcg_temp_free_i32(desc);
  113. + if (!is_store) {
  114. + mark_vs_dirty(s);
  115. + }
  116. gen_set_label(over);
  117. return true;
  118. }
  119. @@ -510,7 +522,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
  120. data = FIELD_DP32(data, VDATA, VM, a->vm);
  121. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  122. data = FIELD_DP32(data, VDATA, NF, a->nf);
  123. - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
  124. + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
  125. }
  126. /*
  127. @@ -562,7 +574,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
  128. data = FIELD_DP32(data, VDATA, VM, a->vm);
  129. data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
  130. data = FIELD_DP32(data, VDATA, NF, a->nf);
  131. - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
  132. + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
  133. }
  134. static bool st_index_check(DisasContext *s, arg_rnfvm* a)
  135. @@ -606,6 +618,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
  136. tcg_temp_free_ptr(mask);
  137. tcg_temp_free(base);
  138. tcg_temp_free_i32(desc);
  139. + mark_vs_dirty(s);
  140. gen_set_label(over);
  141. return true;
  142. }
  143. @@ -685,6 +698,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  144. tcg_temp_free_ptr(index);
  145. tcg_temp_free(base);
  146. tcg_temp_free_i32(desc);
  147. + mark_vs_dirty(s);
  148. gen_set_label(over);
  149. return true;
  150. }
  151. @@ -832,6 +846,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
  152. vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
  153. cpu_env, 0, s->vlen / 8, data, fn);
  154. }
  155. + mark_vs_dirty(s);
  156. gen_set_label(over);
  157. return true;
  158. }
  159. @@ -886,6 +901,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
  160. tcg_temp_free_ptr(src2);
  161. tcg_temp_free(src1);
  162. tcg_temp_free_i32(desc);
  163. + mark_vs_dirty(s);
  164. gen_set_label(over);
  165. return true;
  166. }
  167. @@ -920,6 +936,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
  168. tcg_temp_free_i64(src1);
  169. tcg_temp_free(tmp);
  170. + mark_vs_dirty(s);
  171. return true;
  172. }
  173. return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
  174. @@ -1033,6 +1050,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
  175. tcg_temp_free_ptr(src2);
  176. tcg_temp_free(src1);
  177. tcg_temp_free_i32(desc);
  178. + mark_vs_dirty(s);
  179. gen_set_label(over);
  180. return true;
  181. }
  182. @@ -1056,10 +1074,10 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
  183. gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
  184. sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
  185. }
  186. - } else {
  187. - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
  188. + mark_vs_dirty(s);
  189. + return true;
  190. }
  191. - return true;
  192. + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
  193. }
  194. /* OPIVI with GVEC IR */
  195. @@ -1120,6 +1138,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
  196. vreg_ofs(s, a->rs2),
  197. cpu_env, 0, s->vlen / 8,
  198. data, fn);
  199. + mark_vs_dirty(s);
  200. gen_set_label(over);
  201. return true;
  202. }
  203. @@ -1207,6 +1226,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
  204. vreg_ofs(s, a->rs1),
  205. vreg_ofs(s, a->rs2),
  206. cpu_env, 0, s->vlen / 8, data, fn);
  207. + mark_vs_dirty(s);
  208. gen_set_label(over);
  209. return true;
  210. }
  211. @@ -1285,6 +1305,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  212. vreg_ofs(s, a->rs1), \
  213. vreg_ofs(s, a->rs2), cpu_env, 0, \
  214. s->vlen / 8, data, fns[s->sew]); \
  215. + mark_vs_dirty(s); \
  216. gen_set_label(over); \
  217. return true; \
  218. } \
  219. @@ -1416,6 +1437,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
  220. tcg_temp_free_i32(src1);
  221. tcg_temp_free(tmp);
  222. + mark_vs_dirty(s);
  223. return true;
  224. }
  225. return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
  226. @@ -1474,6 +1496,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  227. vreg_ofs(s, a->rs1), \
  228. vreg_ofs(s, a->rs2), cpu_env, 0, \
  229. s->vlen / 8, data, fns[s->sew]); \
  230. + mark_vs_dirty(s); \
  231. gen_set_label(over); \
  232. return true; \
  233. } \
  234. @@ -1657,6 +1680,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
  235. cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
  236. gen_set_label(over);
  237. }
  238. + mark_vs_dirty(s);
  239. return true;
  240. }
  241. return false;
  242. @@ -1699,6 +1723,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
  243. }
  244. tcg_temp_free(s1);
  245. + mark_vs_dirty(s);
  246. gen_set_label(over);
  247. return true;
  248. }
  249. @@ -1714,6 +1739,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
  250. if (s->vl_eq_vlmax) {
  251. tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
  252. MAXSZ(s), MAXSZ(s), simm);
  253. + mark_vs_dirty(s);
  254. } else {
  255. TCGv_i32 desc;
  256. TCGv_i64 s1;
  257. @@ -1735,6 +1761,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
  258. tcg_temp_free_ptr(dest);
  259. tcg_temp_free_i32(desc);
  260. tcg_temp_free_i64(s1);
  261. + mark_vs_dirty(s);
  262. gen_set_label(over);
  263. }
  264. return true;
  265. @@ -1839,6 +1866,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  266. vreg_ofs(s, a->rs1), \
  267. vreg_ofs(s, a->rs2), cpu_env, 0, \
  268. s->vlen / 8, data, fns[s->sew - 1]); \
  269. + mark_vs_dirty(s); \
  270. gen_set_label(over); \
  271. return true; \
  272. } \
  273. @@ -1874,6 +1902,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
  274. tcg_temp_free_ptr(mask);
  275. tcg_temp_free_ptr(src2);
  276. tcg_temp_free_i32(desc);
  277. + mark_vs_dirty(s);
  278. gen_set_label(over);
  279. return true;
  280. }
  281. @@ -1951,6 +1980,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  282. vreg_ofs(s, a->rs1), \
  283. vreg_ofs(s, a->rs2), cpu_env, 0, \
  284. s->vlen / 8, data, fns[s->sew - 1]); \
  285. + mark_vs_dirty(s); \
  286. gen_set_label(over); \
  287. return true; \
  288. } \
  289. @@ -2025,6 +2055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
  290. vreg_ofs(s, a->rs1), \
  291. vreg_ofs(s, a->rs2), cpu_env, 0, \
  292. s->vlen / 8, data, fns[s->sew - 1]); \
  293. + mark_vs_dirty(s); \
  294. gen_set_label(over); \
  295. return true; \
  296. } \
  297. @@ -2139,6 +2170,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  298. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  299. vreg_ofs(s, a->rs2), cpu_env, 0, \
  300. s->vlen / 8, data, fns[s->sew - 1]); \
  301. + mark_vs_dirty(s); \
  302. gen_set_label(over); \
  303. return true; \
  304. } \
  305. @@ -2211,6 +2243,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
  306. if (s->vl_eq_vlmax) {
  307. tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
  308. MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
  309. + mark_vs_dirty(s);
  310. } else {
  311. TCGv_ptr dest;
  312. TCGv_i32 desc;
  313. @@ -2230,6 +2263,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
  314. tcg_temp_free_ptr(dest);
  315. tcg_temp_free_i32(desc);
  316. + mark_vs_dirty(s);
  317. gen_set_label(over);
  318. }
  319. return true;
  320. @@ -2279,6 +2313,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  321. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  322. vreg_ofs(s, a->rs2), cpu_env, 0, \
  323. s->vlen / 8, data, fns[s->sew - 1]); \
  324. + mark_vs_dirty(s); \
  325. gen_set_label(over); \
  326. return true; \
  327. } \
  328. @@ -2327,6 +2362,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  329. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
  330. vreg_ofs(s, a->rs2), cpu_env, 0, \
  331. s->vlen / 8, data, fns[s->sew - 1]); \
  332. + mark_vs_dirty(s); \
  333. gen_set_label(over); \
  334. return true; \
  335. } \
  336. @@ -2389,6 +2425,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
  337. vreg_ofs(s, a->rs1), \
  338. vreg_ofs(s, a->rs2), cpu_env, 0, \
  339. s->vlen / 8, data, fn); \
  340. + mark_vs_dirty(s); \
  341. gen_set_label(over); \
  342. return true; \
  343. } \
  344. @@ -2486,6 +2523,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
  345. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
  346. vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
  347. cpu_env, 0, s->vlen / 8, data, fn); \
  348. + mark_vs_dirty(s); \
  349. gen_set_label(over); \
  350. return true; \
  351. } \
  352. @@ -2517,6 +2555,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
  353. tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  354. vreg_ofs(s, a->rs2), cpu_env, 0,
  355. s->vlen / 8, data, fns[s->sew]);
  356. + mark_vs_dirty(s);
  357. gen_set_label(over);
  358. return true;
  359. }
  360. @@ -2542,6 +2581,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
  361. };
  362. tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  363. cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
  364. + mark_vs_dirty(s);
  365. gen_set_label(over);
  366. return true;
  367. }
  368. @@ -2717,6 +2757,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
  369. tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
  370. vec_element_storei(s, a->rd, 0, t1);
  371. tcg_temp_free_i64(t1);
  372. + mark_vs_dirty(s);
  373. done:
  374. gen_set_label(over);
  375. return true;
  376. @@ -2767,6 +2808,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
  377. }
  378. vec_element_storei(s, a->rd, 0, t1);
  379. tcg_temp_free_i64(t1);
  380. + mark_vs_dirty(s);
  381. gen_set_label(over);
  382. return true;
  383. }
  384. @@ -2833,6 +2875,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
  385. tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
  386. MAXSZ(s), MAXSZ(s), dest);
  387. tcg_temp_free_i64(dest);
  388. + mark_vs_dirty(s);
  389. } else {
  390. static gen_helper_opivx * const fns[4] = {
  391. gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
  392. @@ -2859,6 +2902,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
  393. endian_ofs(s, a->rs2, a->rs1),
  394. MAXSZ(s), MAXSZ(s));
  395. }
  396. + mark_vs_dirty(s);
  397. } else {
  398. static gen_helper_opivx * const fns[4] = {
  399. gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
  400. @@ -2895,6 +2939,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
  401. tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
  402. vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
  403. cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
  404. + mark_vs_dirty(s);
  405. gen_set_label(over);
  406. return true;
  407. }
  408. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  409. index b199bec4b4..c42c52c90c 100644
  410. --- a/target/riscv/translate.c
  411. +++ b/target/riscv/translate.c
  412. @@ -47,6 +47,7 @@ typedef struct DisasContext {
  413. bool virt_enabled;
  414. uint32_t opcode;
  415. uint32_t mstatus_fs;
  416. + uint32_t mstatus_vs;
  417. uint32_t misa;
  418. uint32_t mem_idx;
  419. /* Remember the rounding mode encoded in the previous fp instruction,
  420. @@ -407,6 +408,37 @@ static void mark_fs_dirty(DisasContext *ctx)
  421. static inline void mark_fs_dirty(DisasContext *ctx) { }
  422. #endif
  423. +#ifndef CONFIG_USER_ONLY
  424. +/* The states of mstatus_vs are:
  425. + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
  426. + * We will have already diagnosed disabled state,
  427. + * and need to turn initial/clean into dirty.
  428. + */
  429. +static void mark_vs_dirty(DisasContext *ctx)
  430. +{
  431. + TCGv tmp;
  432. + if (ctx->mstatus_vs == MSTATUS_VS) {
  433. + return;
  434. + }
  435. + /* Remember the state change for the rest of the TB. */
  436. + ctx->mstatus_vs = MSTATUS_VS;
  437. +
  438. + tmp = tcg_temp_new();
  439. + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
  440. + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD);
  441. + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
  442. +
  443. + if (ctx->virt_enabled) {
  444. + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
  445. + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD);
  446. + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
  447. + }
  448. + tcg_temp_free(tmp);
  449. +}
  450. +#else
  451. +static inline void mark_vs_dirty(DisasContext *ctx) { }
  452. +#endif
  453. +
  454. static void gen_set_rm(DisasContext *ctx, int rm)
  455. {
  456. TCGv_i32 t0;
  457. @@ -644,6 +676,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
  458. ctx->pc_succ_insn = ctx->base.pc_first;
  459. ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
  460. ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
  461. + ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
  462. ctx->priv_ver = env->priv_ver;
  463. #if !defined(CONFIG_USER_ONLY)
  464. if (riscv_has_ext(env, RVH)) {
  465. --
  466. 2.33.1