0013-target-riscv-rvv-1.0-introduce-writable-misa.v-field.patch 1.2 KB

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  1. From 16c565b6660801c6d9b5e83516d61293e957fc9a Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 30 Jul 2020 16:42:55 +0800
  4. Subject: [PATCH 013/107] target/riscv: rvv-1.0: introduce writable misa.v
  5. field
  6. Implementations may have a writable misa.v field. Analogous to the way
  7. in which the floating-point unit is handled, the mstatus.vs field may
  8. exist even if misa.v is clear.
  9. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  10. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  11. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  12. ---
  13. target/riscv/csr.c | 2 +-
  14. 1 file changed, 1 insertion(+), 1 deletion(-)
  15. diff --git a/target/riscv/csr.c b/target/riscv/csr.c
  16. index 2131c12f7f..3a77d2cb86 100644
  17. --- a/target/riscv/csr.c
  18. +++ b/target/riscv/csr.c
  19. @@ -572,7 +572,7 @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
  20. val &= env->misa_mask;
  21. /* Mask extensions that are not supported by QEMU */
  22. - val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
  23. + val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
  24. /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
  25. if ((val & RVD) && !(val & RVF)) {
  26. --
  27. 2.33.1