0012-target-riscv-rvv-1.0-add-sstatus-VS-field.patch 1.7 KB

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  1. From 15d97d2faf70ecb7ec89331cbb4cf651d45824e5 Mon Sep 17 00:00:00 2001
  2. From: LIU Zhiwei <zhiwei_liu@c-sky.com>
  3. Date: Thu, 30 Apr 2020 16:36:09 +0800
  4. Subject: [PATCH 012/107] target/riscv: rvv-1.0: add sstatus VS field
  5. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  9. ---
  10. target/riscv/cpu_bits.h | 1 +
  11. target/riscv/csr.c | 2 +-
  12. 2 files changed, 2 insertions(+), 1 deletion(-)
  13. diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
  14. index f88aae628f..2073abfabf 100644
  15. --- a/target/riscv/cpu_bits.h
  16. +++ b/target/riscv/cpu_bits.h
  17. @@ -415,6 +415,7 @@
  18. #define SSTATUS_UPIE 0x00000010
  19. #define SSTATUS_SPIE 0x00000020
  20. #define SSTATUS_SPP 0x00000100
  21. +#define SSTATUS_VS 0x00000600
  22. #define SSTATUS_FS 0x00006000
  23. #define SSTATUS_XS 0x00018000
  24. #define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
  25. diff --git a/target/riscv/csr.c b/target/riscv/csr.c
  26. index f99fc60bd3..2131c12f7f 100644
  27. --- a/target/riscv/csr.c
  28. +++ b/target/riscv/csr.c
  29. @@ -440,7 +440,7 @@ static const target_ulong delegable_excps =
  30. (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
  31. static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
  32. SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
  33. - SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
  34. + SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD | SSTATUS_VS;
  35. static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
  36. static const target_ulong hip_writable_mask = MIP_VSSIP;
  37. static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
  38. --
  39. 2.33.1