0011-target-riscv-rvv-1.0-add-mstatus-VS-field.patch 6.0 KB

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  1. From 7d7508b495c38f2f1c592ea79183910a31836e30 Mon Sep 17 00:00:00 2001
  2. From: LIU Zhiwei <zhiwei_liu@c-sky.com>
  3. Date: Thu, 16 Jul 2020 02:06:19 +0800
  4. Subject: [PATCH 011/107] target/riscv: rvv-1.0: add mstatus VS field
  5. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
  9. ---
  10. target/riscv/cpu.h | 7 +++++++
  11. target/riscv/cpu_bits.h | 1 +
  12. target/riscv/cpu_helper.c | 15 ++++++++++++++-
  13. target/riscv/csr.c | 25 ++++++++++++++++++++++++-
  14. 4 files changed, 46 insertions(+), 2 deletions(-)
  15. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
  16. index dc4271be2a..8fd7c01567 100644
  17. --- a/target/riscv/cpu.h
  18. +++ b/target/riscv/cpu.h
  19. @@ -336,6 +336,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  20. int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  21. bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
  22. bool riscv_cpu_fp_enabled(CPURISCVState *env);
  23. +bool riscv_cpu_vector_enabled(CPURISCVState *env);
  24. bool riscv_cpu_virt_enabled(CPURISCVState *env);
  25. void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
  26. bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
  27. @@ -382,6 +383,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
  28. #define TB_FLAGS_PRIV_MMU_MASK 3
  29. #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
  30. #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
  31. +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
  32. typedef CPURISCVState CPUArchState;
  33. typedef RISCVCPU ArchCPU;
  34. @@ -437,6 +439,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
  35. #ifdef CONFIG_USER_ONLY
  36. flags |= TB_FLAGS_MSTATUS_FS;
  37. + flags |= TB_FLAGS_MSTATUS_VS;
  38. #else
  39. flags |= cpu_mmu_index(env, 0);
  40. if (riscv_cpu_fp_enabled(env)) {
  41. @@ -451,6 +454,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
  42. flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
  43. }
  44. }
  45. +
  46. + if (riscv_cpu_vector_enabled(env)) {
  47. + flags |= env->mstatus & MSTATUS_VS;
  48. + }
  49. #endif
  50. *pflags = flags;
  51. diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
  52. index caf4599207..f88aae628f 100644
  53. --- a/target/riscv/cpu_bits.h
  54. +++ b/target/riscv/cpu_bits.h
  55. @@ -371,6 +371,7 @@
  56. #define MSTATUS_UBE 0x00000040
  57. #define MSTATUS_MPIE 0x00000080
  58. #define MSTATUS_SPP 0x00000100
  59. +#define MSTATUS_VS 0x00000600
  60. #define MSTATUS_MPP 0x00001800
  61. #define MSTATUS_FS 0x00006000
  62. #define MSTATUS_XS 0x00018000
  63. diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
  64. index 21c54ef561..8605e23a7b 100644
  65. --- a/target/riscv/cpu_helper.c
  66. +++ b/target/riscv/cpu_helper.c
  67. @@ -109,11 +109,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
  68. return false;
  69. }
  70. +/* Return true is vector support is currently enabled */
  71. +bool riscv_cpu_vector_enabled(CPURISCVState *env)
  72. +{
  73. + if (env->mstatus & MSTATUS_VS) {
  74. + if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
  75. + return false;
  76. + }
  77. + return true;
  78. + }
  79. +
  80. + return false;
  81. +}
  82. +
  83. void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
  84. {
  85. uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
  86. MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
  87. - MSTATUS64_UXL;
  88. + MSTATUS64_UXL | MSTATUS_VS;
  89. bool current_virt = riscv_cpu_virt_enabled(env);
  90. g_assert(riscv_has_ext(env, RVH));
  91. diff --git a/target/riscv/csr.c b/target/riscv/csr.c
  92. index d2585395bf..f99fc60bd3 100644
  93. --- a/target/riscv/csr.c
  94. +++ b/target/riscv/csr.c
  95. @@ -260,6 +260,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
  96. return -RISCV_EXCP_ILLEGAL_INST;
  97. }
  98. env->mstatus |= MSTATUS_FS;
  99. + env->mstatus |= MSTATUS_VS;
  100. #endif
  101. env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
  102. if (vs(env, csrno) >= 0) {
  103. @@ -290,6 +291,13 @@ static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
  104. static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
  105. {
  106. +#if !defined(CONFIG_USER_ONLY)
  107. + if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
  108. + return -RISCV_EXCP_ILLEGAL_INST;
  109. + }
  110. + env->mstatus |= MSTATUS_VS;
  111. +#endif
  112. +
  113. env->vxrm = val;
  114. return 0;
  115. }
  116. @@ -302,6 +310,13 @@ static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
  117. static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
  118. {
  119. +#if !defined(CONFIG_USER_ONLY)
  120. + if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
  121. + return -RISCV_EXCP_ILLEGAL_INST;
  122. + }
  123. + env->mstatus |= MSTATUS_VS;
  124. +#endif
  125. +
  126. env->vxsat = val;
  127. return 0;
  128. }
  129. @@ -314,6 +329,13 @@ static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
  130. static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
  131. {
  132. +#if !defined(CONFIG_USER_ONLY)
  133. + if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
  134. + return -RISCV_EXCP_ILLEGAL_INST;
  135. + }
  136. + env->mstatus |= MSTATUS_VS;
  137. +#endif
  138. +
  139. env->vstart = val;
  140. return 0;
  141. }
  142. @@ -478,7 +500,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
  143. mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
  144. MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
  145. MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
  146. - MSTATUS_TW;
  147. + MSTATUS_TW | MSTATUS_VS;
  148. if (!riscv_cpu_is_32bit(env)) {
  149. /*
  150. @@ -491,6 +513,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
  151. mstatus = (mstatus & ~mask) | (val & mask);
  152. dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
  153. + ((mstatus & MSTATUS_VS) == MSTATUS_VS) |
  154. ((mstatus & MSTATUS_XS) == MSTATUS_XS);
  155. mstatus = set_field(mstatus, MSTATUS_SD, dirty);
  156. env->mstatus = mstatus;
  157. --
  158. 2.33.1