0006-fpu-softfloat-set-invalid-excp-flag-for-RISC-V-mulad.patch 1.6 KB

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  1. From 410eaceb105782c98f8d9899c1b316f709a6be5e Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 19 Apr 2021 12:27:56 +0800
  4. Subject: [PATCH 006/107] fpu/softfloat: set invalid excp flag for RISC-V
  5. muladd instructions
  6. In IEEE 754-2008 spec:
  7. Invalid operation exception is signaled when doing:
  8. fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
  9. unless c is a quiet NaN; if c is a quiet NaN then it is
  10. implementation defined whether the invalid operation exception
  11. is signaled.
  12. In RISC-V Unprivileged ISA spec:
  13. The fused multiply-add instructions must set the invalid
  14. operation exception flag when the multiplicands are Inf and
  15. zero, even when the addend is a quiet NaN.
  16. This commit set invalid operation execption flag for RISC-V when
  17. multiplicands of muladd instructions are Inf and zero.
  18. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  19. ---
  20. fpu/softfloat-specialize.c.inc | 6 ++++++
  21. 1 file changed, 6 insertions(+)
  22. diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
  23. index c2f87addb2..12f29fbfc5 100644
  24. --- a/fpu/softfloat-specialize.c.inc
  25. +++ b/fpu/softfloat-specialize.c.inc
  26. @@ -624,6 +624,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
  27. } else {
  28. return 1;
  29. }
  30. +#elif defined(TARGET_RISCV)
  31. + /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
  32. + if (infzero) {
  33. + float_raise(float_flag_invalid, status);
  34. + }
  35. + return 3; /* deafult NaN */
  36. #elif defined(TARGET_XTENSA)
  37. /*
  38. * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
  39. --
  40. 2.33.1