0003-target-riscv-support-x-Zfh-in-cpu-option.patch 1.3 KB

1234567891011121314151617181920212223242526272829303132333435363738
  1. From e14c75b57170fb7f4bfae09a3bd291bc024c3d3c Mon Sep 17 00:00:00 2001
  2. From: Chih-Min Chao <chihmin.chao@sifive.com>
  3. Date: Wed, 1 Jul 2020 21:05:41 -0700
  4. Subject: [PATCH 003/107] target/riscv: support 'x-Zfh' in cpu option
  5. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
  6. ---
  7. target/riscv/cpu.c | 1 +
  8. target/riscv/cpu.h | 1 +
  9. 2 files changed, 2 insertions(+)
  10. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
  11. index 7d6ed80f6b..636d006f80 100644
  12. --- a/target/riscv/cpu.c
  13. +++ b/target/riscv/cpu.c
  14. @@ -545,6 +545,7 @@ static Property riscv_cpu_properties[] = {
  15. /* This is experimental so mark with 'x-' */
  16. DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
  17. DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
  18. + DEFINE_PROP_BOOL("x-Zfh", RISCVCPU, cfg.ext_zfh, false),
  19. DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
  20. DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
  21. DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
  22. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
  23. index 0a33d387ba..6362394204 100644
  24. --- a/target/riscv/cpu.h
  25. +++ b/target/riscv/cpu.h
  26. @@ -295,6 +295,7 @@ struct RISCVCPU {
  27. bool ext_counters;
  28. bool ext_ifencei;
  29. bool ext_icsr;
  30. + bool ext_zfh;
  31. char *priv_spec;
  32. char *user_spec;
  33. --
  34. 2.33.1