0001-merge-riscv-bitmapip-b0p94-version.patch 36 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177
  1. From aff71be69f74519436b9c03ebe17da66934c9b4c Mon Sep 17 00:00:00 2001
  2. From: "eric.tang" <eric.tang@starfivetech.com>
  3. Date: Mon, 27 Sep 2021 16:15:42 +0800
  4. Subject: [PATCH 1/2] merge riscv bitmapip b0p94 version
  5. Signed-off-by: eric.tang <eric.tang@starfivetech.com>
  6. ---
  7. target/riscv/bitmanip_helper.c | 492 +++++++++++++++++++++++-
  8. target/riscv/cpu.c | 2 +-
  9. target/riscv/helper.h | 31 ++
  10. target/riscv/insn32-64.decode | 21 +-
  11. target/riscv/insn32.decode | 63 ++-
  12. target/riscv/insn_trans/trans_rvb.c.inc | 211 +++++++++-
  13. target/riscv/translate.c | 126 +++++-
  14. 7 files changed, 913 insertions(+), 33 deletions(-)
  15. diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
  16. index 389b52eccd..f8de197a67 100644
  17. --- a/target/riscv/bitmanip_helper.c
  18. +++ b/target/riscv/bitmanip_helper.c
  19. @@ -90,13 +90,499 @@ target_ulong HELPER(gorc)(target_ulong rs1, target_ulong rs2)
  20. {
  21. return do_gorc(rs1, rs2, TARGET_LONG_BITS);
  22. }
  23. -
  24. /* RV64-only instruction */
  25. #ifdef TARGET_RISCV64
  26. -
  27. target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong rs2)
  28. {
  29. return do_gorc(rs1, rs2, 32);
  30. }
  31. -
  32. #endif
  33. +
  34. +#define DO_CLMULA(NAME, NUM, BODY) \
  35. +static target_ulong do_##NAME(target_ulong rs1, \
  36. + target_ulong rs2, \
  37. + int bits) \
  38. +{ \
  39. + target_ulong x = 0; \
  40. + int i; \
  41. + \
  42. + for(i = NUM; i < bits; i++) \
  43. + if ((rs2 >> i) & 1) \
  44. + x ^= BODY; \
  45. + \
  46. + return x; \
  47. +}
  48. +
  49. +DO_CLMULA(clmul, 0, (rs1 << i))
  50. +DO_CLMULA(clmulh, 1, (rs1 >> (bits - i)))
  51. +DO_CLMULA(clmulr, 0, (rs1 >> (bits - i - 1)))
  52. +
  53. +target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
  54. +{
  55. + return do_clmul(rs1, rs2, TARGET_LONG_BITS);
  56. +}
  57. +
  58. +target_ulong HELPER(clmulh)(target_ulong rs1, target_ulong rs2)
  59. +{
  60. + return do_clmulh(rs1, rs2, TARGET_LONG_BITS);
  61. +}
  62. +
  63. +target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
  64. +{
  65. + return do_clmulr(rs1, rs2, TARGET_LONG_BITS);
  66. +}
  67. +
  68. +static target_ulong do_cmov(target_ulong rs1,
  69. + target_ulong rs2,
  70. + target_ulong rs3)
  71. +{
  72. + return rs2 ? rs1 : rs3;
  73. +}
  74. +
  75. +target_ulong HELPER(cmov)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  76. +{
  77. + return do_cmov(rs1, rs2, rs3);
  78. +}
  79. +
  80. +static target_ulong do_fsl(target_ulong rs1,
  81. + target_ulong rs2,
  82. + target_ulong rs3,
  83. + int bits)
  84. +{
  85. + int shamt = rs2 & (2*bits - 1);
  86. + target_ulong a = rs1, b = rs3;
  87. +
  88. + if (shamt >= bits) {
  89. + shamt -= bits;
  90. + a = rs3;
  91. + b = rs1;
  92. + }
  93. +
  94. + return shamt ? (a << shamt) | (b >> (bits - shamt)) : a;
  95. +}
  96. +
  97. +target_ulong HELPER(fsl)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  98. +{
  99. + return do_fsl(rs1, rs2, rs3, TARGET_LONG_BITS);
  100. +}
  101. +
  102. +target_ulong HELPER(fsr)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  103. +{
  104. + return do_fsl(rs1, -rs2, rs3, TARGET_LONG_BITS);
  105. +}
  106. +
  107. +static target_ulong do_fslw(target_ulong rs1,
  108. + target_ulong rs2,
  109. + target_ulong rs3)
  110. +{
  111. + int shamt = rs2 & 63;
  112. + target_ulong a = rs1, b = rs3;
  113. +
  114. + if (shamt >= 32) {
  115. + shamt -= 32;
  116. + a = rs3;
  117. + b = rs1;
  118. + }
  119. +
  120. + return shamt ? (a << shamt) | ((b & 0xffffffff) >> (32 - shamt)) : a;
  121. +}
  122. +
  123. +target_ulong HELPER(fslw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  124. +{
  125. + return do_fslw(rs1, rs2, rs3);
  126. +}
  127. +
  128. +target_ulong HELPER(fsrw)(target_ulong rs1, target_ulong rs2, target_ulong rs3)
  129. +{
  130. + return do_fslw(rs1, -rs2, rs3);
  131. +}
  132. +
  133. +static target_ulong do_shfl(target_ulong rs1,
  134. + target_ulong rs2,
  135. + int bits)
  136. +{
  137. + target_ulong x = rs1;
  138. + int shamt = rs2 & ((bits-1) >> 1);
  139. + if (shamt & 16)
  140. + x = (x & 0xFFFF00000000FFFFLL) |
  141. + ((x & 0x0000FFFF00000000LL) >> 16) |
  142. + ((x & 0x00000000FFFF0000LL) << 16);
  143. + if (shamt & 8)
  144. + x = (x & 0xFF0000FFFF0000FFLL) |
  145. + ((x & 0x00FF000000FF0000LL) >> 8) |
  146. + ((x & 0x0000FF000000FF00LL) << 8);
  147. + if (shamt & 4)
  148. + x = (x & 0xF00FF00FF00FF00FLL) |
  149. + ((x & 0x0F000F000F000F00LL) >> 4) |
  150. + ((x & 0x00F000F000F000F0LL) << 4);
  151. + if (shamt & 2)
  152. + x = (x & 0xC3C3C3C3C3C3C3C3LL) |
  153. + ((x & 0x3030303030303030LL) >> 2) |
  154. + ((x & 0x0C0C0C0C0C0C0C0CLL) << 2);
  155. + if (shamt & 1)
  156. + x = (x & 0x9999999999999999LL) |
  157. + ((x & 0x4444444444444444LL) >> 1) |
  158. + ((x & 0x2222222222222222LL) << 1);
  159. +
  160. + return x;
  161. +}
  162. +
  163. +static target_ulong do_unshfl(target_ulong rs1,
  164. + target_ulong rs2,
  165. + int bits)
  166. +{
  167. + target_ulong x = rs1;
  168. +
  169. + int shamt = rs2 & ((bits-1) >> 1);
  170. + if (shamt & 1)
  171. + x = (x & 0x9999999999999999LL) |
  172. + ((x & 0x4444444444444444LL) >> 1) |
  173. + ((x & 0x2222222222222222LL) << 1);
  174. + if (shamt & 2)
  175. + x = (x & 0xC3C3C3C3C3C3C3C3LL) |
  176. + ((x & 0x3030303030303030LL) >> 2) |
  177. + ((x & 0x0C0C0C0C0C0C0C0CLL) << 2);
  178. + if (shamt & 4)
  179. + x = (x & 0xF00FF00FF00FF00FLL) |
  180. + ((x & 0x0F000F000F000F00LL) >> 4) |
  181. + ((x & 0x00F000F000F000F0LL) << 4);
  182. + if (shamt & 8)
  183. + x = (x & 0xFF0000FFFF0000FFLL) |
  184. + ((x & 0x00FF000000FF0000LL) >> 8) |
  185. + ((x & 0x0000FF000000FF00LL) << 8);
  186. + if (shamt & 16)
  187. + x = (x & 0xFFFF00000000FFFFLL) |
  188. + ((x & 0x0000FFFF00000000LL) >> 16) |
  189. + ((x & 0x00000000FFFF0000LL) << 16);
  190. +
  191. + return x;
  192. +}
  193. +
  194. +static target_ulong do_shflw(target_ulong rs1,
  195. + target_ulong rs2)
  196. +{
  197. + target_ulong x = rs1;
  198. + int shamt = rs2 & 15;
  199. + if (shamt & 8)
  200. + x = (x & 0xFF0000FFFF0000FFLL) |
  201. + ((x & 0x00FF000000FF0000LL) >> 8) |
  202. + ((x & 0x0000FF000000FF00LL) << 8);
  203. + if (shamt & 4)
  204. + x = (x & 0xF00FF00FF00FF00FLL) |
  205. + ((x & 0x0F000F000F000F00LL) >> 4) |
  206. + ((x & 0x00F000F000F000F0LL) << 4);
  207. + if (shamt & 2)
  208. + x = (x & 0xC3C3C3C3C3C3C3C3LL) |
  209. + ((x & 0x3030303030303030LL) >> 2) |
  210. + ((x & 0x0C0C0C0C0C0C0C0CLL) << 2);
  211. + if (shamt & 1)
  212. + x = (x & 0x9999999999999999LL) |
  213. + ((x & 0x4444444444444444LL) >> 1) |
  214. + ((x & 0x2222222222222222LL) << 1);
  215. +
  216. + return x;
  217. +}
  218. +
  219. +static target_ulong do_unshflw(target_ulong rs1,
  220. + target_ulong rs2)
  221. +{
  222. + target_ulong x = rs1;
  223. + int shamt = rs2 & 15;
  224. + if (shamt & 1)
  225. + x = (x & 0x9999999999999999LL) |
  226. + ((x & 0x4444444444444444LL) >> 1) |
  227. + ((x & 0x2222222222222222LL) << 1);
  228. + if (shamt & 2)
  229. + x = (x & 0xC3C3C3C3C3C3C3C3LL) |
  230. + ((x & 0x3030303030303030LL) >> 2) |
  231. + ((x & 0x0C0C0C0C0C0C0C0CLL) << 2);
  232. + if (shamt & 4)
  233. + x = (x & 0xF00FF00FF00FF00FLL) |
  234. + ((x & 0x0F000F000F000F00LL) >> 4) |
  235. + ((x & 0x00F000F000F000F0LL) << 4);
  236. + if (shamt & 8)
  237. + x = (x & 0xFF0000FFFF0000FFLL) |
  238. + ((x & 0x00FF000000FF0000LL) >> 8) |
  239. + ((x & 0x0000FF000000FF00LL) << 8);
  240. +
  241. + return x;
  242. +}
  243. +
  244. +target_ulong HELPER(shfl)(target_ulong rs1, target_ulong rs2)
  245. +{
  246. + return do_shfl(rs1, rs2, TARGET_LONG_BITS);
  247. +}
  248. +
  249. +target_ulong HELPER(unshfl)(target_ulong rs1, target_ulong rs2)
  250. +{
  251. + return do_unshfl(rs1, rs2, TARGET_LONG_BITS);
  252. +}
  253. +
  254. +target_ulong HELPER(shflw)(target_ulong rs1, target_ulong rs2)
  255. +{
  256. + return do_shflw(rs1, rs2);
  257. +}
  258. +
  259. +target_ulong HELPER(unshflw)(target_ulong rs1, target_ulong rs2)
  260. +{
  261. + return do_unshflw(rs1, rs2);
  262. +}
  263. +
  264. +static target_ulong do_xperm(target_ulong rs1,
  265. + target_ulong rs2,
  266. + int sz_log2,
  267. + int bits)
  268. +{
  269. + target_ulong pos = 0;
  270. + target_ulong r = 0;
  271. + target_ulong sz = 1LL << sz_log2;
  272. + target_ulong mask = (1LL << sz) - 1;
  273. + int i;
  274. + for (i = 0; i < bits; i += sz) {
  275. + pos = ((rs2 >> i) & mask) << sz_log2;
  276. + if (pos < bits)
  277. + r |= ((rs1 >> pos) & mask) << i;
  278. + }
  279. +
  280. + return r;
  281. +}
  282. +
  283. +target_ulong HELPER(xperm_n)(target_ulong rs1, target_ulong rs2)
  284. +{
  285. + return do_xperm(rs1, rs2, 2, TARGET_LONG_BITS);
  286. +}
  287. +
  288. +target_ulong HELPER(xperm_b)(target_ulong rs1, target_ulong rs2)
  289. +{
  290. + return do_xperm(rs1, rs2, 3, TARGET_LONG_BITS);
  291. +}
  292. +
  293. +target_ulong HELPER(xperm_h)(target_ulong rs1, target_ulong rs2)
  294. +{
  295. + return do_xperm(rs1, rs2, 4, TARGET_LONG_BITS);
  296. +}
  297. +
  298. +target_ulong HELPER(xperm_w)(target_ulong rs1, target_ulong rs2)
  299. +{
  300. + return do_xperm(rs1, rs2, 5, TARGET_LONG_BITS);
  301. +}
  302. +
  303. +static target_ulong do_bfp(target_ulong rs1,
  304. + target_ulong rs2,
  305. + int bits)
  306. +{
  307. + target_ulong cfg = rs2 >> (bits/2);
  308. + if ((cfg >> 30) == 2)
  309. + cfg = cfg >> 16;
  310. + int len = (cfg >> 8) & (bits/2 - 1);
  311. + int off = cfg & (bits - 1);
  312. + len = len ? len : bits/2;
  313. + target_ulong mask = ~(~(target_ulong)0 << len) << off;
  314. + target_ulong data = rs2 << off;
  315. +
  316. + return (data & mask) | (rs1 & ~mask);
  317. +}
  318. +
  319. +static target_ulong do_bfpw(target_ulong rs1,
  320. + target_ulong rs2)
  321. +{
  322. + target_ulong cfg = rs2 >> 16;
  323. + int len = (cfg >> 8) & 15;
  324. + int off = cfg & 31;
  325. + len = len ? len : 16;
  326. + target_ulong mask = ~(~(target_ulong)(0) << len) << off;
  327. + target_ulong data = rs2 << off;
  328. +
  329. + return (data & mask) | (rs1 & ~mask);
  330. +}
  331. +
  332. +target_ulong HELPER(bfp)(target_ulong rs1, target_ulong rs2)
  333. +{
  334. + return do_bfp(rs1, rs2, TARGET_LONG_BITS);
  335. +}
  336. +
  337. +target_ulong HELPER(bfpw)(target_ulong rs1, target_ulong rs2)
  338. +{
  339. + return do_bfpw(rs1, rs2);
  340. +}
  341. +
  342. +static target_ulong do_bcompress(target_ulong rs1,
  343. + target_ulong rs2,
  344. + int bits)
  345. +{
  346. + target_ulong r = 0;
  347. + int i, j = 0;
  348. + for (i = 0; i < bits; i++) {
  349. + if ((rs2 >> i) & 1) {
  350. + if ((rs1 >> i) & 1)
  351. + r |= (target_ulong)1 << j;
  352. + j++;
  353. + }
  354. + }
  355. +
  356. + return r;
  357. +}
  358. +
  359. +static target_ulong do_bdecompress(target_ulong rs1,
  360. + target_ulong rs2,
  361. + int bits)
  362. +{
  363. + target_ulong r = 0;
  364. + int i, j = 0;
  365. + for (i = 0; i < bits; i++) {
  366. + if ((rs2 >> i) & 1) {
  367. + if ((rs1 >> j) & 1)
  368. + r |= (target_ulong)1 << i;
  369. + j++;
  370. + }
  371. + }
  372. +
  373. + return r;
  374. +}
  375. +
  376. +target_ulong HELPER(bcompress)(target_ulong rs1, target_ulong rs2)
  377. +{
  378. + return do_bcompress(rs1, rs2, TARGET_LONG_BITS);
  379. +}
  380. +
  381. +target_ulong HELPER(bdecompress)(target_ulong rs1, target_ulong rs2)
  382. +{
  383. + return do_bdecompress(rs1, rs2, TARGET_LONG_BITS);
  384. +}
  385. +
  386. +#define DO_CRC(NAME, VALUE) \
  387. +static target_ulong do_##NAME(target_ulong rs1, \
  388. + int nbits) \
  389. +{ \
  390. + int i; \
  391. + target_ulong x = rs1; \
  392. + for (i = 0; i < nbits; i++) \
  393. + x = (x >> 1) ^ ((VALUE) & ~((x&1)-1)); \
  394. + return x; \
  395. +}
  396. +
  397. +DO_CRC(crc32, 0xEDB88320)
  398. +DO_CRC(crc32c, 0x82F63B78)
  399. +
  400. +target_ulong HELPER(crc32_b)(target_ulong rs1)
  401. +{
  402. + return do_crc32(rs1, 8);
  403. +}
  404. +
  405. +target_ulong HELPER(crc32_h)(target_ulong rs1)
  406. +{
  407. + return do_crc32(rs1, 16);
  408. +}
  409. +
  410. +target_ulong HELPER(crc32_w)(target_ulong rs1)
  411. +{
  412. + return do_crc32(rs1, 32);
  413. +}
  414. +
  415. +target_ulong HELPER(crc32_d)(target_ulong rs1)
  416. +{
  417. + return do_crc32(rs1, 64);
  418. +}
  419. +
  420. +target_ulong HELPER(crc32c_b)(target_ulong rs1)
  421. +{
  422. + return do_crc32c(rs1, 8);
  423. +}
  424. +
  425. +target_ulong HELPER(crc32c_h)(target_ulong rs1)
  426. +{
  427. + return do_crc32c(rs1, 16);
  428. +}
  429. +
  430. +target_ulong HELPER(crc32c_w)(target_ulong rs1)
  431. +{
  432. + return do_crc32c(rs1, 32);
  433. +}
  434. +
  435. +target_ulong HELPER(crc32c_d)(target_ulong rs1)
  436. +{
  437. + return do_crc32c(rs1, 64);
  438. +}
  439. +
  440. +static inline uint64_t popcount(uint64_t val)
  441. +{
  442. + val = (val & 0x5555555555555555U) + ((val >> 1) & 0x5555555555555555U);
  443. + val = (val & 0x3333333333333333U) + ((val >> 2) & 0x3333333333333333U);
  444. + val = (val & 0x0f0f0f0f0f0f0f0fU) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fU);
  445. + val = (val & 0x00ff00ff00ff00ffU) + ((val >> 8) & 0x00ff00ff00ff00ffU);
  446. + val = (val & 0x0000ffff0000ffffU) + ((val >> 16) & 0x0000ffff0000ffffU);
  447. + val = (val & 0x00000000ffffffffU) + ((val >> 32) & 0x00000000ffffffffU);
  448. + return val;
  449. +}
  450. +
  451. +static target_ulong do_bmatflip(target_ulong rs1,
  452. + int bits)
  453. +{
  454. + target_ulong x = rs1;
  455. + for (int i = 0; i < 3; i++)
  456. + x = do_shfl(x, 31, bits);
  457. + return x;
  458. +}
  459. +
  460. +static target_ulong do_bmatxor(target_ulong rs1,
  461. + target_ulong rs2,
  462. + int bits)
  463. +{
  464. + int i;
  465. + uint8_t u[8];
  466. + uint8_t v[8];
  467. + uint64_t x = 0;
  468. +
  469. + target_ulong rs2t = do_bmatflip(rs2, bits);
  470. +
  471. + for (i = 0; i < 8; i++) {
  472. + u[i] = rs1 >> (i * 8);
  473. + v[i] = rs2t >> (i * 8);
  474. + }
  475. +
  476. + for (int i = 0; i < 64; i++) {
  477. + if (popcount(u[i / 8] & v[i % 8]) & 1)
  478. + x |= 1LL << i;
  479. + }
  480. +
  481. + return x;
  482. +}
  483. +
  484. +static target_ulong do_bmator(target_ulong rs1,
  485. + target_ulong rs2,
  486. + int bits)
  487. +{
  488. + int i;
  489. + uint8_t u[8];
  490. + uint8_t v[8];
  491. + uint64_t x = 0;
  492. +
  493. + target_ulong rs2t = do_bmatflip(rs2, bits);
  494. +
  495. + for (i = 0; i < 8; i++) {
  496. + u[i] = rs1 >> (i * 8);
  497. + v[i] = rs2t >> (i * 8);
  498. + }
  499. +
  500. + for (int i = 0; i < 64; i++) {
  501. + if ((u[i / 8] & v[i % 8]) != 0)
  502. + x |= 1LL << i;
  503. + }
  504. +
  505. + return x;
  506. +}
  507. +
  508. +target_ulong HELPER(bmatflip)(target_ulong rs1)
  509. +{
  510. + return do_bmatflip(rs1, TARGET_LONG_BITS);
  511. +}
  512. +
  513. +target_ulong HELPER(bmatxor)(target_ulong rs1, target_ulong rs2)
  514. +{
  515. + return do_bmatxor(rs1, rs2, TARGET_LONG_BITS);
  516. +}
  517. +
  518. +target_ulong HELPER(bmator)(target_ulong rs1, target_ulong rs2)
  519. +{
  520. + return do_bmator(rs1, rs2, TARGET_LONG_BITS);
  521. +}
  522. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
  523. index b6713855d6..1b22fb0f3a 100644
  524. --- a/target/riscv/cpu.c
  525. +++ b/target/riscv/cpu.c
  526. @@ -152,7 +152,7 @@ static void set_resetvec(CPURISCVState *env, int resetvec)
  527. static void riscv_any_cpu_init(Object *obj)
  528. {
  529. CPURISCVState *env = &RISCV_CPU(obj)->env;
  530. - set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
  531. + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU);
  532. set_priv_version(env, PRIV_VERSION_1_11_0);
  533. }
  534. diff --git a/target/riscv/helper.h b/target/riscv/helper.h
  535. index 9bbf93d47e..9f0abef25f 100644
  536. --- a/target/riscv/helper.h
  537. +++ b/target/riscv/helper.h
  538. @@ -100,6 +100,37 @@ DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  539. DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  540. DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  541. #endif
  542. +DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  543. +DEF_HELPER_FLAGS_2(clmulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  544. +DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  545. +DEF_HELPER_FLAGS_2(shfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  546. +DEF_HELPER_FLAGS_2(unshfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  547. +DEF_HELPER_FLAGS_2(shflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  548. +DEF_HELPER_FLAGS_2(unshflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  549. +DEF_HELPER_FLAGS_2(xperm_n, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  550. +DEF_HELPER_FLAGS_2(xperm_b, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  551. +DEF_HELPER_FLAGS_2(xperm_h, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  552. +DEF_HELPER_FLAGS_2(xperm_w, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  553. +DEF_HELPER_FLAGS_2(bfp, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  554. +DEF_HELPER_FLAGS_2(bfpw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  555. +DEF_HELPER_FLAGS_2(bcompress, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  556. +DEF_HELPER_FLAGS_2(bdecompress, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  557. +DEF_HELPER_FLAGS_2(bmatxor, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  558. +DEF_HELPER_FLAGS_2(bmator, TCG_CALL_NO_RWG_SE, tl, tl, tl)
  559. +DEF_HELPER_FLAGS_1(bmatflip, TCG_CALL_NO_RWG_SE, tl, tl)
  560. +DEF_HELPER_FLAGS_1(crc32_b, TCG_CALL_NO_RWG_SE, tl, tl)
  561. +DEF_HELPER_FLAGS_1(crc32_h, TCG_CALL_NO_RWG_SE, tl, tl)
  562. +DEF_HELPER_FLAGS_1(crc32_w, TCG_CALL_NO_RWG_SE, tl, tl)
  563. +DEF_HELPER_FLAGS_1(crc32_d, TCG_CALL_NO_RWG_SE, tl, tl)
  564. +DEF_HELPER_FLAGS_1(crc32c_b, TCG_CALL_NO_RWG_SE, tl, tl)
  565. +DEF_HELPER_FLAGS_1(crc32c_h, TCG_CALL_NO_RWG_SE, tl, tl)
  566. +DEF_HELPER_FLAGS_1(crc32c_w, TCG_CALL_NO_RWG_SE, tl, tl)
  567. +DEF_HELPER_FLAGS_1(crc32c_d, TCG_CALL_NO_RWG_SE, tl, tl)
  568. +DEF_HELPER_FLAGS_3(cmov, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  569. +DEF_HELPER_FLAGS_3(fsl, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  570. +DEF_HELPER_FLAGS_3(fsr, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  571. +DEF_HELPER_FLAGS_3(fslw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  572. +DEF_HELPER_FLAGS_3(fsrw, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
  573. /* Special functions */
  574. DEF_HELPER_3(csrrw, tl, env, tl, tl)
  575. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  576. index 2c3313531f..b5ab197edc 100644
  577. --- a/target/riscv/insn32-64.decode
  578. +++ b/target/riscv/insn32-64.decode
  579. @@ -21,7 +21,11 @@
  580. %sh5 20:5
  581. -@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
  582. +
  583. +# Formats 64:
  584. +@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
  585. +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
  586. +@r3w_imm ..... . ...... ..... ... ..... ....... &r3i %rs3 imm=%sh5 %rs1 %rd
  587. # *** RV64I Base Instruction Set (in addition to RV32I) ***
  588. lwu ............ ..... 110 ..... 0000011 @i
  589. @@ -93,11 +97,17 @@ fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
  590. fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
  591. fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
  592. +
  593. # *** RV64B Standard Extension (in addition to RV32B) ***
  594. clzw 0110000 00000 ..... 001 ..... 0011011 @r2
  595. ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
  596. cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
  597. +crc32_d 0110000 10011 ..... 001 ..... 0010011 @r2
  598. +crc32c_d 0110000 11011 ..... 001 ..... 0010011 @r2
  599. +bmatflip 011000 000011 ..... 001 ..... 0010011 @r2
  600. +bmator 0000100 .......... 011 ..... 0110011 @r
  601. +bmatxor 0100100 .......... 011 ..... 0110011 @r
  602. packw 0000100 .......... 100 ..... 0111011 @r
  603. packuw 0100100 .......... 100 ..... 0111011 @r
  604. bsetw 0010100 .......... 001 ..... 0111011 @r
  605. @@ -114,7 +124,16 @@ sh1add_uw 0010000 .......... 010 ..... 0111011 @r
  606. sh2add_uw 0010000 .......... 100 ..... 0111011 @r
  607. sh3add_uw 0010000 .......... 110 ..... 0111011 @r
  608. add_uw 0000100 .......... 000 ..... 0111011 @r
  609. +shflw 0000100 .......... 001 ..... 0111011 @r
  610. +unshflw 0000100 .......... 101 ..... 0111011 @r
  611. +xperm_w 0010100 .......... 000 ..... 0110011 @r
  612. +bfpw 0100100 .......... 111 ..... 0111011 @r
  613. +fslw .....10 .......... 001 ..... 0111011 @r3
  614. +fsrw .....10 .......... 101 ..... 0111011 @r3
  615. +bcompressw 0000100 .......... 110 ..... 0111011 @r
  616. +bdecompressw 0100100 .......... 110 ..... 0111011 @r
  617. +fsriw .....10 .......... 101 ..... 0011011 @r3w_imm
  618. bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  619. bclriw 0100100 .......... 001 ..... 0011011 @sh5
  620. binviw 0110100 .......... 001 ..... 0011011 @sh5
  621. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  622. index 9a45f2265b..f4b030747c 100644
  623. --- a/target/riscv/insn32.decode
  624. +++ b/target/riscv/insn32.decode
  625. @@ -23,6 +23,7 @@
  626. %rd 7:5
  627. %sh7 20:7
  628. +%sh6 20:6
  629. %csr 20:12
  630. %rm 12:3
  631. %nf 29:3 !function=ex_plus_1
  632. @@ -41,6 +42,8 @@
  633. &j imm rd
  634. &r rd rs1 rs2
  635. &r2 rd rs1
  636. +&r3 rd rs1 rs2 rs3
  637. +&r3i rd rs1 imm rs3
  638. &s imm rs1 rs2
  639. &u imm rd
  640. &shift shamt rs1 rd
  641. @@ -59,12 +62,16 @@
  642. @u .................... ..... ....... &u imm=%imm_u %rd
  643. @j .................... ..... ....... &j imm=%imm_j %rd
  644. -@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
  645. +
  646. +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
  647. @csr ............ ..... ... ..... ....... %csr %rs1 %rd
  648. @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
  649. @atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
  650. +@r3 ..... .. ..... ..... ... ..... ....... &r3 %rs3 %rs2 %rs1 %rd
  651. +@r3_imm ..... . ...... ..... ... ..... ....... &r3i %rs3 imm=%sh6 %rs1 %rd
  652. +
  653. @r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
  654. @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
  655. @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
  656. @@ -124,9 +131,9 @@ sltiu ............ ..... 011 ..... 0010011 @i
  657. xori ............ ..... 100 ..... 0010011 @i
  658. ori ............ ..... 110 ..... 0010011 @i
  659. andi ............ ..... 111 ..... 0010011 @i
  660. -slli 00000. ...... ..... 001 ..... 0010011 @sh
  661. -srli 00000. ...... ..... 101 ..... 0010011 @sh
  662. -srai 01000. ...... ..... 101 ..... 0010011 @sh
  663. +slli 000000 ...... ..... 001 ..... 0010011 @sh6
  664. +srli 000000 ...... ..... 101 ..... 0010011 @sh6
  665. +srai 010000 ...... ..... 101 ..... 0010011 @sh6
  666. add 0000000 ..... ..... 000 ..... 0110011 @r
  667. sub 0100000 ..... ..... 000 ..... 0110011 @r
  668. sll 0000000 ..... ..... 001 ..... 0110011 @r
  669. @@ -694,8 +701,17 @@ fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
  670. clz 011000 000000 ..... 001 ..... 0010011 @r2
  671. ctz 011000 000001 ..... 001 ..... 0010011 @r2
  672. cpop 011000 000010 ..... 001 ..... 0010011 @r2
  673. +
  674. sext_b 011000 000100 ..... 001 ..... 0010011 @r2
  675. sext_h 011000 000101 ..... 001 ..... 0010011 @r2
  676. +crc32_b 0110000 10000 ..... 001 ..... 0010011 @r2
  677. +crc32_h 0110000 10001 ..... 001 ..... 0010011 @r2
  678. +crc32_w 0110000 10010 ..... 001 ..... 0010011 @r2
  679. +
  680. +crc32c_b 0110000 11000 ..... 001 ..... 0010011 @r2
  681. +crc32c_h 0110000 11001 ..... 001 ..... 0010011 @r2
  682. +crc32c_w 0110000 11010 ..... 001 ..... 0010011 @r2
  683. +
  684. andn 0100000 .......... 111 ..... 0110011 @r
  685. orn 0100000 .......... 110 ..... 0110011 @r
  686. @@ -720,13 +736,34 @@ gorc 0010100 .......... 101 ..... 0110011 @r
  687. sh1add 0010000 .......... 010 ..... 0110011 @r
  688. sh2add 0010000 .......... 100 ..... 0110011 @r
  689. sh3add 0010000 .......... 110 ..... 0110011 @r
  690. +clmul 0000101 .......... 001 ..... 0110011 @r
  691. +clmulh 0000101 .......... 011 ..... 0110011 @r
  692. +clmulr 0000101 .......... 010 ..... 0110011 @r
  693. +shfl 0000100 .......... 001 ..... 0110011 @r
  694. +unshfl 0000100 .......... 101 ..... 0110011 @r
  695. +xperm_n 0010100 .......... 010 ..... 0110011 @r
  696. +xperm_b 0010100 .......... 100 ..... 0110011 @r
  697. +xperm_h 0010100 .......... 110 ..... 0110011 @r
  698. +bfp 0100100 .......... 111 ..... 0110011 @r
  699. +cmix .....11 .......... 001 ..... 0110011 @r3
  700. +cmov .....11 .......... 101 ..... 0110011 @r3
  701. +fsl .....10 .......... 001 ..... 0110011 @r3
  702. +fsr .....10 .......... 101 ..... 0110011 @r3
  703. +bcompress 0000100 .......... 110 ..... 0110011 @r
  704. +bdecompress 0100100 .......... 110 ..... 0110011 @r
  705. +
  706. +
  707. +fsri .....1 ........... 101 ..... 0010011 @r3_imm
  708. +bseti 001010 ........... 001 ..... 0010011 @sh6
  709. +bclri 010010 ........... 001 ..... 0010011 @sh6
  710. +binvi 011010 ........... 001 ..... 0010011 @sh6
  711. +bexti 010010 ........... 101 ..... 0010011 @sh6
  712. +sloi 001000 ........... 001 ..... 0010011 @sh6
  713. +sroi 001000 ........... 101 ..... 0010011 @sh6
  714. +rori 011000 ........... 101 ..... 0010011 @sh6
  715. +grevi 011010 ........... 101 ..... 0010011 @sh6
  716. +gorci 001010 ........... 101 ..... 0010011 @sh6
  717. +shfli 000010 ........... 001 ..... 0010011 @sh6
  718. +unshfli 000010 ........... 101 ..... 0010011 @sh6
  719. +
  720. -bseti 00101. ........... 001 ..... 0010011 @sh
  721. -bclri 01001. ........... 001 ..... 0010011 @sh
  722. -binvi 01101. ........... 001 ..... 0010011 @sh
  723. -bexti 01001. ........... 101 ..... 0010011 @sh
  724. -sloi 00100. ........... 001 ..... 0010011 @sh
  725. -sroi 00100. ........... 101 ..... 0010011 @sh
  726. -rori 01100. ........... 101 ..... 0010011 @sh
  727. -grevi 01101. ........... 101 ..... 0010011 @sh
  728. -gorci 00101. ........... 101 ..... 0010011 @sh
  729. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  730. index d69bda2f7b..394277b02f 100644
  731. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  732. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  733. @@ -237,8 +237,210 @@ GEN_TRANS_SHADD(1)
  734. GEN_TRANS_SHADD(2)
  735. GEN_TRANS_SHADD(3)
  736. +
  737. +#define GEN_TRANS_CLMUL(NAME) \
  738. +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
  739. +{ \
  740. + REQUIRE_EXT(ctx, RVB); \
  741. + return gen_arith(ctx, a, gen_helper_##NAME); \
  742. +}
  743. +
  744. +GEN_TRANS_CLMUL(clmul)
  745. +GEN_TRANS_CLMUL(clmulh)
  746. +GEN_TRANS_CLMUL(clmulr)
  747. +
  748. +static bool trans_shfl(DisasContext *ctx, arg_shfl *a)
  749. +{
  750. + REQUIRE_EXT(ctx, RVB);
  751. + return gen_arith(ctx, a, gen_helper_shfl);
  752. +}
  753. +
  754. +static bool trans_unshfl(DisasContext *ctx, arg_unshfl *a)
  755. +{
  756. + REQUIRE_EXT(ctx, RVB);
  757. + return gen_arith(ctx, a, gen_helper_unshfl);
  758. +}
  759. +
  760. +static bool trans_shfli(DisasContext *ctx, arg_shfli *a)
  761. +{
  762. + REQUIRE_EXT(ctx, RVB);
  763. + if (a->shamt >= (TARGET_LONG_BITS / 2)) {
  764. + return false;
  765. + }
  766. + return gen_shifti(ctx, a, gen_helper_shfl);
  767. +}
  768. +
  769. +static bool trans_unshfli(DisasContext *ctx, arg_unshfli *a)
  770. +{
  771. + REQUIRE_EXT(ctx, RVB);
  772. + if (a->shamt >= (TARGET_LONG_BITS / 2)) {
  773. + return false;
  774. + }
  775. + return gen_shifti(ctx, a, gen_helper_unshfl);
  776. +}
  777. +
  778. +#define GEN_TRANS_XPERM(NAME) \
  779. +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
  780. +{ \
  781. + REQUIRE_EXT(ctx, RVB); \
  782. + return gen_arith(ctx, a, gen_helper_##NAME); \
  783. +}
  784. +
  785. +GEN_TRANS_XPERM(xperm_n)
  786. +GEN_TRANS_XPERM(xperm_b)
  787. +GEN_TRANS_XPERM(xperm_h)
  788. +
  789. +static bool trans_bfp(DisasContext *ctx, arg_bfp *a)
  790. +{
  791. + REQUIRE_EXT(ctx, RVB);
  792. + return gen_arith(ctx, a, gen_helper_bfp);
  793. +}
  794. +
  795. +static bool trans_bcompress(DisasContext *ctx, arg_bcompress *a)
  796. +{
  797. + REQUIRE_EXT(ctx, RVB);
  798. + return gen_arith(ctx, a, gen_helper_bcompress);
  799. +}
  800. +
  801. +static bool trans_bdecompress(DisasContext *ctx, arg_bdecompress *a)
  802. +{
  803. + REQUIRE_EXT(ctx, RVB);
  804. + return gen_arith(ctx, a, gen_helper_bdecompress);
  805. +}
  806. +
  807. +static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
  808. +{
  809. + REQUIRE_EXT(ctx, RVB);
  810. + return gen_quat(ctx, a, gen_cmix);
  811. +}
  812. +
  813. +static bool trans_cmov(DisasContext *ctx, arg_cmov *a)
  814. +{
  815. + REQUIRE_EXT(ctx, RVB);
  816. + return gen_quat(ctx, a, gen_helper_cmov);
  817. +}
  818. +
  819. +static bool trans_fsl(DisasContext *ctx, arg_fsl *a)
  820. +{
  821. + REQUIRE_EXT(ctx, RVB);
  822. + return gen_quat(ctx, a, gen_helper_fsl);
  823. +}
  824. +
  825. +static bool trans_fsr(DisasContext *ctx, arg_fsr *a)
  826. +{
  827. + REQUIRE_EXT(ctx, RVB);
  828. + return gen_quat(ctx, a, gen_helper_fsr);
  829. +}
  830. +
  831. +static bool trans_fsri(DisasContext *ctx, arg_fsri *a)
  832. +{
  833. + REQUIRE_EXT(ctx, RVB);
  834. +
  835. + if (a->imm >= 64) {
  836. + return false;
  837. + }
  838. +
  839. + return gen_quati(ctx, a, gen_helper_fsr);
  840. +}
  841. +
  842. +/* RV64-only instructions */
  843. +#ifdef TARGET_RISCV64
  844. +static bool trans_shflw(DisasContext *ctx, arg_shflw *a)
  845. +{
  846. + REQUIRE_EXT(ctx, RVB);
  847. + return gen_arith(ctx, a, gen_shflw);
  848. +}
  849. +
  850. +static bool trans_unshflw(DisasContext *ctx, arg_unshflw *a)
  851. +{
  852. + REQUIRE_EXT(ctx, RVB);
  853. + return gen_arith(ctx, a, gen_unshflw);
  854. +}
  855. +
  856. +static bool trans_xperm_w(DisasContext *ctx, arg_xperm_w *a)
  857. +{
  858. + REQUIRE_EXT(ctx, RVB);
  859. + return gen_arith(ctx, a, gen_helper_xperm_w);
  860. +}
  861. +
  862. +static bool trans_bfpw(DisasContext *ctx, arg_bfpw *a)
  863. +{
  864. + REQUIRE_EXT(ctx, RVB);
  865. + return gen_arith(ctx, a, gen_bfpw);
  866. +}
  867. +
  868. +static bool trans_fslw(DisasContext *ctx, arg_fslw *a)
  869. +{
  870. + REQUIRE_EXT(ctx, RVB);
  871. + return gen_quat(ctx, a, gen_fslw);
  872. +}
  873. +
  874. +static bool trans_fsrw(DisasContext *ctx, arg_fsrw *a)
  875. +{
  876. + REQUIRE_EXT(ctx, RVB);
  877. + return gen_quat(ctx, a, gen_fsrw);
  878. +}
  879. +
  880. +static bool trans_fsriw(DisasContext *ctx, arg_fsri *a)
  881. +{
  882. + REQUIRE_EXT(ctx, RVB);
  883. +
  884. + if (a->imm >= 32) {
  885. + return false;
  886. + }
  887. +
  888. + return gen_quati(ctx, a, gen_fsrw);
  889. +}
  890. +
  891. +static bool trans_bcompressw(DisasContext *ctx, arg_bcompressw *a)
  892. +{
  893. + REQUIRE_EXT(ctx, RVB);
  894. + return gen_arith(ctx, a, gen_bcompressw);
  895. +}
  896. +
  897. +static bool trans_bdecompressw(DisasContext *ctx, arg_bdecompressw *a)
  898. +{
  899. + REQUIRE_EXT(ctx, RVB);
  900. + return gen_arith(ctx, a, gen_bdecompressw);
  901. +}
  902. +#endif
  903. +
  904. +#define GEN_TRANS_CRC(NAME) \
  905. +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
  906. +{ \
  907. + REQUIRE_EXT(ctx, RVB); \
  908. + return gen_unary(ctx, a, gen_helper_##NAME); \
  909. +} \
  910. +
  911. +GEN_TRANS_CRC(crc32_b)
  912. +GEN_TRANS_CRC(crc32_h)
  913. +GEN_TRANS_CRC(crc32_w)
  914. +
  915. +GEN_TRANS_CRC(crc32c_b)
  916. +GEN_TRANS_CRC(crc32c_h)
  917. +GEN_TRANS_CRC(crc32c_w)
  918. /* RV64-only instructions */
  919. #ifdef TARGET_RISCV64
  920. +GEN_TRANS_CRC(crc32c_d)
  921. +GEN_TRANS_CRC(crc32_d)
  922. +
  923. +static bool trans_bmatflip(DisasContext *ctx, arg_bmatflip *a)
  924. +{
  925. + REQUIRE_EXT(ctx, RVB);
  926. + return gen_unary(ctx, a, gen_helper_bmatflip);
  927. +}
  928. +
  929. +static bool trans_bmatxor(DisasContext *ctx, arg_bmatxor *a)
  930. +{
  931. + REQUIRE_EXT(ctx, RVB);
  932. + return gen_arith(ctx, a, gen_helper_bmatxor);
  933. +}
  934. +
  935. +static bool trans_bmator(DisasContext *ctx, arg_bmatxor *a)
  936. +{
  937. + REQUIRE_EXT(ctx, RVB);
  938. + return gen_arith(ctx, a, gen_helper_bmator);
  939. +}
  940. static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
  941. {
  942. @@ -327,13 +529,13 @@ static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
  943. static bool trans_srow(DisasContext *ctx, arg_srow *a)
  944. {
  945. REQUIRE_EXT(ctx, RVB);
  946. - return gen_shiftw(ctx, a, gen_sro);
  947. + return gen_shiftw(ctx, a, gen_srow);
  948. }
  949. static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
  950. {
  951. REQUIRE_EXT(ctx, RVB);
  952. - return gen_shiftiw(ctx, a, gen_sro);
  953. + return gen_shiftiw(ctx, a, gen_srow);
  954. }
  955. static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  956. @@ -404,14 +606,13 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
  957. gen_get_gpr(source1, a->rs1);
  958. if (a->shamt < 32) {
  959. - tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32);
  960. + tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
  961. } else {
  962. - tcg_gen_shli_i64(source1, source1, a->shamt);
  963. + tcg_gen_shli_tl(source1, source1, a->shamt);
  964. }
  965. gen_set_gpr(a->rd, source1);
  966. tcg_temp_free(source1);
  967. return true;
  968. }
  969. -
  970. #endif
  971. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  972. index 744b4ffaa7..8c581d1ccf 100644
  973. --- a/target/riscv/translate.c
  974. +++ b/target/riscv/translate.c
  975. @@ -731,15 +731,15 @@ GEN_SHADD(3)
  976. static void gen_ctzw(TCGv ret, TCGv arg1)
  977. {
  978. - tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
  979. - tcg_gen_ctzi_i64(ret, ret, 64);
  980. + tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
  981. + tcg_gen_ctzi_tl(ret, ret, 64);
  982. }
  983. static void gen_clzw(TCGv ret, TCGv arg1)
  984. {
  985. - tcg_gen_ext32u_i64(ret, arg1);
  986. - tcg_gen_clzi_i64(ret, ret, 64);
  987. - tcg_gen_subi_i64(ret, ret, 32);
  988. + tcg_gen_ext32u_tl(ret, arg1);
  989. + tcg_gen_clzi_tl(ret, ret, 64);
  990. + tcg_gen_subi_tl(ret, ret, 32);
  991. }
  992. static void gen_cpopw(TCGv ret, TCGv arg1)
  993. @@ -751,17 +751,17 @@ static void gen_cpopw(TCGv ret, TCGv arg1)
  994. static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
  995. {
  996. TCGv t = tcg_temp_new();
  997. - tcg_gen_ext16s_i64(t, arg2);
  998. - tcg_gen_deposit_i64(ret, arg1, t, 16, 48);
  999. + tcg_gen_ext16s_tl(t, arg2);
  1000. + tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
  1001. tcg_temp_free(t);
  1002. }
  1003. static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
  1004. {
  1005. TCGv t = tcg_temp_new();
  1006. - tcg_gen_shri_i64(t, arg1, 16);
  1007. - tcg_gen_deposit_i64(ret, arg2, t, 0, 16);
  1008. - tcg_gen_ext32s_i64(ret, ret);
  1009. + tcg_gen_shri_tl(t, arg1, 16);
  1010. + tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
  1011. + tcg_gen_ext32s_tl(ret, ret);
  1012. tcg_temp_free(t);
  1013. }
  1014. @@ -801,6 +801,26 @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
  1015. tcg_temp_free_i32(t2);
  1016. }
  1017. +static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2)
  1018. +{
  1019. + TCGv_i32 t1 = tcg_temp_new_i32();
  1020. + TCGv_i32 t2 = tcg_temp_new_i32();
  1021. +
  1022. + /* truncate to 32-bits */
  1023. + tcg_gen_trunc_tl_i32(t1, arg1);
  1024. + tcg_gen_trunc_tl_i32(t2, arg2);
  1025. +
  1026. + tcg_gen_not_i32(t1, t1);
  1027. + tcg_gen_shr_i32(t1, t1, t2);
  1028. + tcg_gen_not_i32(t1, t1);
  1029. +
  1030. + /* sign-extend 64-bits */
  1031. + tcg_gen_ext_i32_tl(ret, t1);
  1032. +
  1033. + tcg_temp_free_i32(t1);
  1034. + tcg_temp_free_i32(t2);
  1035. +}
  1036. +
  1037. static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
  1038. {
  1039. tcg_gen_ext32u_tl(arg1, arg1);
  1040. @@ -836,6 +856,42 @@ static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
  1041. tcg_gen_add_tl(ret, arg1, arg2);
  1042. }
  1043. +#define GEN_RV64ONLY_INSN_3(NAME) \
  1044. +static void gen_##NAME(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3) \
  1045. +{ \
  1046. + gen_helper_##NAME(ret, arg1, arg2, arg3); \
  1047. + tcg_gen_ext32s_tl(ret, ret); \
  1048. +} \
  1049. +
  1050. +GEN_RV64ONLY_INSN_3(fslw)
  1051. +GEN_RV64ONLY_INSN_3(fsrw)
  1052. +
  1053. +#define GEN_RV64ONLY_INSN_2(NAME) \
  1054. +static void gen_##NAME(TCGv ret, TCGv arg1, TCGv arg2) \
  1055. +{ \
  1056. + gen_helper_##NAME(ret, arg1, arg2); \
  1057. + tcg_gen_ext32s_tl(ret, ret); \
  1058. +} \
  1059. +
  1060. +GEN_RV64ONLY_INSN_2(shflw)
  1061. +GEN_RV64ONLY_INSN_2(unshflw)
  1062. +GEN_RV64ONLY_INSN_2(bfpw)
  1063. +
  1064. +static void gen_bcompressw(TCGv ret, TCGv arg1, TCGv arg2)
  1065. +{
  1066. + tcg_gen_ext32u_tl(arg1, arg1);
  1067. + tcg_gen_ext32u_tl(arg2, arg2);
  1068. + gen_helper_bcompress(ret, arg1, arg2);
  1069. + tcg_gen_ext32s_tl(ret, ret);
  1070. +}
  1071. +
  1072. +static void gen_bdecompressw(TCGv ret, TCGv arg1, TCGv arg2)
  1073. +{
  1074. + tcg_gen_ext32u_tl(arg1, arg1);
  1075. + tcg_gen_ext32u_tl(arg2, arg2);
  1076. + gen_helper_bdecompress(ret, arg1, arg2);
  1077. + tcg_gen_ext32s_tl(ret, ret);
  1078. +}
  1079. #endif
  1080. static bool gen_arith(DisasContext *ctx, arg_r *a,
  1081. @@ -856,6 +912,35 @@ static bool gen_arith(DisasContext *ctx, arg_r *a,
  1082. return true;
  1083. }
  1084. +static void gen_cmix(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
  1085. +{
  1086. + tcg_gen_and_tl(arg1, arg1, arg2);
  1087. + tcg_gen_not_tl(arg2, arg2);
  1088. + tcg_gen_and_tl(arg3, arg3, arg2);
  1089. + tcg_gen_or_tl(ret, arg1, arg3);
  1090. +}
  1091. +
  1092. +static bool gen_quat(DisasContext *ctx, arg_r3 *a,
  1093. + void(*func)(TCGv, TCGv, TCGv, TCGv))
  1094. +{
  1095. + TCGv source1, source2, source3;
  1096. + source1 = tcg_temp_new();
  1097. + source2 = tcg_temp_new();
  1098. + source3 = tcg_temp_new();
  1099. +
  1100. + gen_get_gpr(source1, a->rs1);
  1101. + gen_get_gpr(source2, a->rs2);
  1102. + gen_get_gpr(source3, a->rs3);
  1103. +
  1104. + (*func)(source1, source1, source2, source3);
  1105. +
  1106. + gen_set_gpr(a->rd, source1);
  1107. + tcg_temp_free(source1);
  1108. + tcg_temp_free(source2);
  1109. + tcg_temp_free(source3);
  1110. + return true;
  1111. +}
  1112. +
  1113. static bool gen_shift(DisasContext *ctx, arg_r *a,
  1114. void(*func)(TCGv, TCGv, TCGv))
  1115. {
  1116. @@ -874,6 +959,27 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
  1117. return true;
  1118. }
  1119. +static bool gen_quati(DisasContext *ctx, arg_r3i *a,
  1120. + void(*func)(TCGv, TCGv, TCGv, TCGv))
  1121. +{
  1122. + TCGv source1, source2, source3;
  1123. + source1 = tcg_temp_new();
  1124. + source2 = tcg_temp_new();
  1125. + source3 = tcg_temp_new();
  1126. +
  1127. + gen_get_gpr(source1, a->rs1);
  1128. + tcg_gen_movi_tl(source2, a->imm);
  1129. + gen_get_gpr(source3, a->rs3);
  1130. +
  1131. + (*func)(source1, source1, source2, source3);
  1132. +
  1133. + gen_set_gpr(a->rd, source1);
  1134. + tcg_temp_free(source1);
  1135. + tcg_temp_free(source2);
  1136. + tcg_temp_free(source3);
  1137. + return true;
  1138. +}
  1139. +
  1140. static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  1141. {
  1142. DisasContext *ctx = container_of(dcbase, DisasContext, base);
  1143. --
  1144. 2.33.1