0001-RISCV-enable-align-loops-8-for-optimized-func.patch 6.7 KB

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  1. From 1199d8653f9c8e6f7d197a040f83e6374bcb376c Mon Sep 17 00:00:00 2001
  2. From: "demin.han" <demin.han@starfivetech.com>
  3. Date: Wed, 15 Mar 2023 15:29:14 +0800
  4. Subject: [PATCH 1/2] [RISCV] enable align-loops=8 for optimized func
  5. ---
  6. sysdeps/riscv/rv64/multiarch/memchr_as.S | 1 +
  7. sysdeps/riscv/rv64/multiarch/memcmp_as.S | 6 ++----
  8. sysdeps/riscv/rv64/multiarch/memcpy_as.S | 2 ++
  9. sysdeps/riscv/rv64/multiarch/memmove_as.S | 6 ++++--
  10. sysdeps/riscv/rv64/multiarch/memrchr.S | 1 +
  11. sysdeps/riscv/rv64/multiarch/memset_as.S | 2 +-
  12. sysdeps/riscv/rv64/multiarch/strcmp_as.S | 2 +-
  13. sysdeps/riscv/rv64/multiarch/strlen_as.S | 2 +-
  14. sysdeps/riscv/rv64/strchr.S | 1 +
  15. sysdeps/riscv/rv64/strchrnul.S | 1 +
  16. sysdeps/riscv/rv64/strncmp.S | 1 +
  17. sysdeps/riscv/rv64/strnlen.S | 2 +-
  18. 12 files changed, 17 insertions(+), 10 deletions(-)
  19. diff --git a/sysdeps/riscv/rv64/multiarch/memchr_as.S b/sysdeps/riscv/rv64/multiarch/memchr_as.S
  20. index 4d3221c60e..1294562e1b 100644
  21. --- a/sysdeps/riscv/rv64/multiarch/memchr_as.S
  22. +++ b/sysdeps/riscv/rv64/multiarch/memchr_as.S
  23. @@ -55,6 +55,7 @@ ENTRY (__memchr)
  24. slli a3, a1, 32
  25. or a1, a1, a3
  26. li a5, -1
  27. + .p2align 3
  28. .L_loop:
  29. ld a3, 0(a0)
  30. xor a3, a3, a1
  31. diff --git a/sysdeps/riscv/rv64/multiarch/memcmp_as.S b/sysdeps/riscv/rv64/multiarch/memcmp_as.S
  32. index 972f6cb5fd..8e8fd680d6 100644
  33. --- a/sysdeps/riscv/rv64/multiarch/memcmp_as.S
  34. +++ b/sysdeps/riscv/rv64/multiarch/memcmp_as.S
  35. @@ -57,6 +57,7 @@ ENTRY (memcmp)
  36. andi t5, a1, 0x7
  37. andi a2, a2, (16-1)
  38. bnez t5, .L_merge
  39. + .p2align 3
  40. .L_loop:
  41. ld a3, 0(a1)
  42. ld a0, 0(a5)
  43. @@ -99,9 +100,6 @@ ENTRY (memcmp)
  44. li a0, 0
  45. ret
  46. - .balign 4
  47. - .option push
  48. - .option norvc
  49. .L_merge:
  50. andi a1, a1, -8
  51. ld t2, 0(a1)
  52. @@ -109,6 +107,7 @@ ENTRY (memcmp)
  53. neg t4, t3
  54. andi t4, t4, (64 - 1)
  55. srl t1, t2, t3
  56. + .p2align 3
  57. 1:
  58. ld t2, 8(a1)
  59. sll a3, t2, t4
  60. @@ -123,7 +122,6 @@ ENTRY (memcmp)
  61. ld a0, 8(a5)
  62. bne a3, a0, .L_end
  63. srl t1, t2, t3
  64. - .option pop
  65. addi a5, a5, 16
  66. addi a1, a1, 16
  67. diff --git a/sysdeps/riscv/rv64/multiarch/memcpy_as.S b/sysdeps/riscv/rv64/multiarch/memcpy_as.S
  68. index fae522684c..35419d2f9f 100644
  69. --- a/sysdeps/riscv/rv64/multiarch/memcpy_as.S
  70. +++ b/sysdeps/riscv/rv64/multiarch/memcpy_as.S
  71. @@ -78,6 +78,7 @@ ENTRY (memcpy)
  72. andi a4, a2, -32
  73. beqz a4, .L_tail
  74. add a4, a4, a5
  75. + .p2align 3
  76. .L_loop:
  77. copy_32B a5, a1
  78. addi a5, a5, 32
  79. @@ -121,6 +122,7 @@ ENTRY (memcpy)
  80. neg t4, t3
  81. andi t4, t4, (64 - 1)
  82. srl t1, t2, t3
  83. + .p2align 3
  84. 1:
  85. ld t2, 8(a1)
  86. sll a3, t2, t4
  87. diff --git a/sysdeps/riscv/rv64/multiarch/memmove_as.S b/sysdeps/riscv/rv64/multiarch/memmove_as.S
  88. index 35d0905186..b859f9778d 100644
  89. --- a/sysdeps/riscv/rv64/multiarch/memmove_as.S
  90. +++ b/sysdeps/riscv/rv64/multiarch/memmove_as.S
  91. @@ -58,6 +58,7 @@ ENTRY (memmove)
  92. andi a2, a2, (32 - 1)
  93. beqz a4, .L_8B_fwd
  94. add a4, a4, a5
  95. + .p2align 3
  96. 0:
  97. ld a3, 0(a1)
  98. sd a3, 0(a5)
  99. @@ -102,7 +103,6 @@ ENTRY (memmove)
  100. .L_ret_fwd:
  101. ret
  102. - .balign 4
  103. .L_merge_fwd:
  104. andi a4, a2, -8
  105. beqz a4, .L_byte_tail_fwd
  106. @@ -113,6 +113,7 @@ ENTRY (memmove)
  107. neg t4, t3
  108. andi t4, t4, (64 - 1)
  109. srl t1, t2, t3
  110. + .p2align 3
  111. 1:
  112. ld t2, 8(a1)
  113. sll a3, t2, t4
  114. @@ -149,6 +150,7 @@ ENTRY (memmove)
  115. andi a2, a2, (32 - 1)
  116. beqz a4, .L_8B_bwd
  117. sub a4, a5, a4
  118. + .p2align 3
  119. 0:
  120. addi a5, a5, -32
  121. addi a1, a1, -32
  122. @@ -193,7 +195,6 @@ ENTRY (memmove)
  123. .L_ret_bwd:
  124. ret
  125. - .balign 4
  126. .L_merge_bwd:
  127. andi a4, a2, -8
  128. beqz a4, .L_byte_tail_bwd
  129. @@ -204,6 +205,7 @@ ENTRY (memmove)
  130. neg t4, t3
  131. andi t4, t4, (64 - 1)
  132. sll t1, t2, t4
  133. + .p2align 3
  134. 1:
  135. ld t2, -8(a1)
  136. srl a3, t2, t3
  137. diff --git a/sysdeps/riscv/rv64/multiarch/memrchr.S b/sysdeps/riscv/rv64/multiarch/memrchr.S
  138. index b72a13e62a..223db0702a 100644
  139. --- a/sysdeps/riscv/rv64/multiarch/memrchr.S
  140. +++ b/sysdeps/riscv/rv64/multiarch/memrchr.S
  141. @@ -59,6 +59,7 @@ ENTRY (MEMRCHR)
  142. slli a3, a1, 32
  143. or a1, a1, a3
  144. li a5, -1
  145. + .p2align 3
  146. .L_loop:
  147. ld a3, -8(a0)
  148. xor a3, a3, a1
  149. diff --git a/sysdeps/riscv/rv64/multiarch/memset_as.S b/sysdeps/riscv/rv64/multiarch/memset_as.S
  150. index 455033adf0..0793237051 100644
  151. --- a/sysdeps/riscv/rv64/multiarch/memset_as.S
  152. +++ b/sysdeps/riscv/rv64/multiarch/memset_as.S
  153. @@ -63,7 +63,7 @@ ENTRY (memset)
  154. andi a4, a2, -64
  155. beqz a4, .L_tail
  156. add a4, a4, a5
  157. -
  158. + .p2align 3
  159. .L_loop:
  160. sd a1, 0(a5)
  161. sd a1, 8(a5)
  162. diff --git a/sysdeps/riscv/rv64/multiarch/strcmp_as.S b/sysdeps/riscv/rv64/multiarch/strcmp_as.S
  163. index 40bdbfef08..e23eb9f74c 100644
  164. --- a/sysdeps/riscv/rv64/multiarch/strcmp_as.S
  165. +++ b/sysdeps/riscv/rv64/multiarch/strcmp_as.S
  166. @@ -57,7 +57,7 @@ ENTRY (strcmp)
  167. ret
  168. .endif
  169. .endm
  170. -
  171. +.p2align 3
  172. .Lloop:
  173. add a0, a0, N*8
  174. add a1, a1, N*8
  175. diff --git a/sysdeps/riscv/rv64/multiarch/strlen_as.S b/sysdeps/riscv/rv64/multiarch/strlen_as.S
  176. index 862f5ebb72..9601ab2b11 100644
  177. --- a/sysdeps/riscv/rv64/multiarch/strlen_as.S
  178. +++ b/sysdeps/riscv/rv64/multiarch/strlen_as.S
  179. @@ -36,7 +36,7 @@ ENTRY (strlen)
  180. addi a3, a1, 8
  181. li a4, -1
  182. - .align 2
  183. + .p2align 3
  184. .Lloop:
  185. ld a2, 8(a1)
  186. addi a1, a1, 8
  187. diff --git a/sysdeps/riscv/rv64/strchr.S b/sysdeps/riscv/rv64/strchr.S
  188. index 2d108800c1..dfeec6da7e 100644
  189. --- a/sysdeps/riscv/rv64/strchr.S
  190. +++ b/sysdeps/riscv/rv64/strchr.S
  191. @@ -41,6 +41,7 @@ ENTRY (strchr)
  192. li a5, -1
  193. addi a0, a0, -8
  194. + .p2align 3
  195. .Lloop:
  196. addi a0, a0, 8
  197. ld a2, 0(a0)
  198. diff --git a/sysdeps/riscv/rv64/strchrnul.S b/sysdeps/riscv/rv64/strchrnul.S
  199. index 3e48445f11..6cf125cf46 100644
  200. --- a/sysdeps/riscv/rv64/strchrnul.S
  201. +++ b/sysdeps/riscv/rv64/strchrnul.S
  202. @@ -41,6 +41,7 @@ ENTRY (__strchrnul)
  203. li a5, -1
  204. addi a0, a0, -8
  205. + .p2align 3
  206. .Lloop:
  207. addi a0, a0, 8
  208. ld a2, 0(a0)
  209. diff --git a/sysdeps/riscv/rv64/strncmp.S b/sysdeps/riscv/rv64/strncmp.S
  210. index 85245df98d..200bee4fe1 100644
  211. --- a/sysdeps/riscv/rv64/strncmp.S
  212. +++ b/sysdeps/riscv/rv64/strncmp.S
  213. @@ -27,6 +27,7 @@ ENTRY (strncmp)
  214. beqz a4, .Lenter
  215. j .Lmisaligned
  216. + .p2align 3
  217. .Lloop:
  218. addi a0, a0, 8
  219. addi a1, a1, 8
  220. diff --git a/sysdeps/riscv/rv64/strnlen.S b/sysdeps/riscv/rv64/strnlen.S
  221. index 73757b69f2..502f108710 100644
  222. --- a/sysdeps/riscv/rv64/strnlen.S
  223. +++ b/sysdeps/riscv/rv64/strnlen.S
  224. @@ -37,7 +37,7 @@ ENTRY (__strnlen)
  225. beqz a4, .Llenth
  226. addi a5, a5, 1
  227. j .Lmisaligned
  228. -
  229. +.p2align 3
  230. .Laligned:
  231. addi a5, a5, 8
  232. addi a1, a1, -8
  233. --
  234. 2.25.1