0101-target-riscv-rvb-add-b-ext-version-cpu-option.patch 3.5 KB

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  1. From 117409c92aec3105a1b4ffeac465c3b06cfc5f29 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Mon, 19 Apr 2021 16:44:08 +0800
  4. Subject: [PATCH 101/107] target/riscv: rvb: add b-ext version cpu option
  5. Default b-ext version is v0.93.
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. ---
  8. target/riscv/cpu.c | 23 +++++++++++++++++++++++
  9. target/riscv/cpu.h | 3 +++
  10. 2 files changed, 26 insertions(+)
  11. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
  12. index b0519793ed..b6713855d6 100644
  13. --- a/target/riscv/cpu.c
  14. +++ b/target/riscv/cpu.c
  15. @@ -127,6 +127,11 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
  16. env->priv_ver = priv_ver;
  17. }
  18. +static void set_bext_version(CPURISCVState *env, int bext_ver)
  19. +{
  20. + env->bext_ver = bext_ver;
  21. +}
  22. +
  23. static void set_vext_version(CPURISCVState *env, int vext_ver)
  24. {
  25. env->vext_ver = vext_ver;
  26. @@ -380,6 +385,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  27. CPURISCVState *env = &cpu->env;
  28. RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
  29. int priv_version = PRIV_VERSION_1_11_0;
  30. + int bext_version = BEXT_VERSION_0_93_0;
  31. int vext_version = VEXT_VERSION_1_00_0;
  32. target_ulong target_misa = env->misa;
  33. Error *local_err = NULL;
  34. @@ -404,6 +410,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  35. }
  36. set_priv_version(env, priv_version);
  37. + set_bext_version(env, bext_version);
  38. set_vext_version(env, vext_version);
  39. if (cpu->cfg.mmu) {
  40. @@ -475,6 +482,21 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
  41. }
  42. if (cpu->cfg.ext_b) {
  43. target_misa |= RVB;
  44. +
  45. + if (cpu->cfg.bext_spec) {
  46. + if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
  47. + bext_version = BEXT_VERSION_0_93_0;
  48. + } else {
  49. + error_setg(errp,
  50. + "Unsupported bitmanip spec version '%s'",
  51. + cpu->cfg.bext_spec);
  52. + return;
  53. + }
  54. + } else {
  55. + qemu_log("bitmanip version is not specified, "
  56. + "use the default value v0.93\n");
  57. + }
  58. + set_bext_version(env, bext_version);
  59. }
  60. if (cpu->cfg.ext_v) {
  61. target_misa |= RVV;
  62. @@ -554,6 +576,7 @@ static Property riscv_cpu_properties[] = {
  63. DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
  64. DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
  65. DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
  66. + DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
  67. DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
  68. DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
  69. DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
  70. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
  71. index 457d95eff1..a6f68473fb 100644
  72. --- a/target/riscv/cpu.h
  73. +++ b/target/riscv/cpu.h
  74. @@ -87,6 +87,7 @@ enum {
  75. #define PRIV_VERSION_1_10_0 0x00011000
  76. #define PRIV_VERSION_1_11_0 0x00011100
  77. +#define BEXT_VERSION_0_93_0 0x00009300
  78. #define VEXT_VERSION_1_00_0 0x00010000
  79. enum {
  80. @@ -136,6 +137,7 @@ struct CPURISCVState {
  81. target_ulong guest_phys_fault_addr;
  82. target_ulong priv_ver;
  83. + target_ulong bext_ver;
  84. target_ulong vext_ver;
  85. target_ulong misa;
  86. target_ulong misa_mask;
  87. @@ -304,6 +306,7 @@ struct RISCVCPU {
  88. char *priv_spec;
  89. char *user_spec;
  90. + char *bext_spec;
  91. char *vext_spec;
  92. uint16_t vlen;
  93. uint16_t elen;
  94. --
  95. 2.33.1