0099-target-riscv-rvb-add-shift-with-prefix-zero-extend.patch 2.7 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485
  1. From 4dc841cbfcaff84840ecd7c5595f436b4387e019 Mon Sep 17 00:00:00 2001
  2. From: Kito Cheng <kito.cheng@sifive.com>
  3. Date: Tue, 20 Oct 2020 18:31:24 +0800
  4. Subject: [PATCH 099/107] target/riscv: rvb: add/shift with prefix zero-extend
  5. Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32-64.decode | 3 +++
  10. target/riscv/insn_trans/trans_rvb.c.inc | 24 ++++++++++++++++++++++++
  11. target/riscv/translate.c | 6 ++++++
  12. 3 files changed, 33 insertions(+)
  13. diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
  14. index d4fa4498be..2c3313531f 100644
  15. --- a/target/riscv/insn32-64.decode
  16. +++ b/target/riscv/insn32-64.decode
  17. @@ -113,6 +113,7 @@ gorcw 0010100 .......... 101 ..... 0111011 @r
  18. sh1add_uw 0010000 .......... 010 ..... 0111011 @r
  19. sh2add_uw 0010000 .......... 100 ..... 0111011 @r
  20. sh3add_uw 0010000 .......... 110 ..... 0111011 @r
  21. +add_uw 0000100 .......... 000 ..... 0111011 @r
  22. bsetiw 0010100 .......... 001 ..... 0011011 @sh5
  23. bclriw 0100100 .......... 001 ..... 0011011 @sh5
  24. @@ -122,3 +123,5 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5
  25. roriw 0110000 .......... 101 ..... 0011011 @sh5
  26. greviw 0110100 .......... 101 ..... 0011011 @sh5
  27. gorciw 0010100 .......... 101 ..... 0011011 @sh5
  28. +
  29. +slli_uw 00001. ........... 001 ..... 0011011 @sh
  30. diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
  31. index ca987f2705..d69bda2f7b 100644
  32. --- a/target/riscv/insn_trans/trans_rvb.c.inc
  33. +++ b/target/riscv/insn_trans/trans_rvb.c.inc
  34. @@ -390,4 +390,28 @@ GEN_TRANS_SHADD_UW(1)
  35. GEN_TRANS_SHADD_UW(2)
  36. GEN_TRANS_SHADD_UW(3)
  37. +static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
  38. +{
  39. + REQUIRE_EXT(ctx, RVB);
  40. + return gen_arith(ctx, a, gen_add_uw);
  41. +}
  42. +
  43. +static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
  44. +{
  45. + REQUIRE_EXT(ctx, RVB);
  46. +
  47. + TCGv source1 = tcg_temp_new();
  48. + gen_get_gpr(source1, a->rs1);
  49. +
  50. + if (a->shamt < 32) {
  51. + tcg_gen_deposit_z_i64(source1, source1, a->shamt, 32);
  52. + } else {
  53. + tcg_gen_shli_i64(source1, source1, a->shamt);
  54. + }
  55. +
  56. + gen_set_gpr(a->rd, source1);
  57. + tcg_temp_free(source1);
  58. + return true;
  59. +}
  60. +
  61. #endif
  62. diff --git a/target/riscv/translate.c b/target/riscv/translate.c
  63. index f02ab479aa..171cf6bb08 100644
  64. --- a/target/riscv/translate.c
  65. +++ b/target/riscv/translate.c
  66. @@ -820,6 +820,12 @@ GEN_SHADD_UW(1)
  67. GEN_SHADD_UW(2)
  68. GEN_SHADD_UW(3)
  69. +static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
  70. +{
  71. + tcg_gen_ext32u_tl(arg1, arg1);
  72. + tcg_gen_add_tl(ret, arg1, arg2);
  73. +}
  74. +
  75. #endif
  76. static bool gen_arith(DisasContext *ctx, arg_r *a,
  77. --
  78. 2.33.1