0065-target-riscv-rvv-1.0-remove-integer-extract-instruct.patch 2.5 KB

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  1. From 04eef9250669b0efaa4fa93d975562d18616c9d8 Mon Sep 17 00:00:00 2001
  2. From: Frank Chang <frank.chang@sifive.com>
  3. Date: Thu, 2 Jul 2020 16:16:35 +0800
  4. Subject: [PATCH 065/107] target/riscv: rvv-1.0: remove integer extract
  5. instruction
  6. Signed-off-by: Frank Chang <frank.chang@sifive.com>
  7. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
  8. ---
  9. target/riscv/insn32.decode | 1 -
  10. target/riscv/insn_trans/trans_rvv.c.inc | 23 -----------------------
  11. 2 files changed, 24 deletions(-)
  12. diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
  13. index d6b9adf9aa..8794397c74 100644
  14. --- a/target/riscv/insn32.decode
  15. +++ b/target/riscv/insn32.decode
  16. @@ -607,7 +607,6 @@ viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
  17. vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
  18. vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
  19. vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
  20. -vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
  21. vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
  22. vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
  23. vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
  24. diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
  25. index 215dd55bc9..8cc79f1228 100644
  26. --- a/target/riscv/insn_trans/trans_rvv.c.inc
  27. +++ b/target/riscv/insn_trans/trans_rvv.c.inc
  28. @@ -3071,8 +3071,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
  29. *** Vector Permutation Instructions
  30. */
  31. -/* Integer Extract Instruction */
  32. -
  33. static void load_element(TCGv_i64 dest, TCGv_ptr base,
  34. int ofs, int sew, bool sign)
  35. {
  36. @@ -3174,27 +3172,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
  37. load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
  38. }
  39. -static bool trans_vext_x_v(DisasContext *s, arg_r *a)
  40. -{
  41. - TCGv_i64 tmp = tcg_temp_new_i64();
  42. - TCGv dest = tcg_temp_new();
  43. -
  44. - if (a->rs1 == 0) {
  45. - /* Special case vmv.x.s rd, vs2. */
  46. - vec_element_loadi(s, tmp, a->rs2, 0, false);
  47. - } else {
  48. - /* This instruction ignores LMUL and vector register groups */
  49. - int vlmax = s->vlen >> (3 + s->sew);
  50. - vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
  51. - }
  52. - tcg_gen_trunc_i64_tl(dest, tmp);
  53. - gen_set_gpr(a->rd, dest);
  54. -
  55. - tcg_temp_free(dest);
  56. - tcg_temp_free_i64(tmp);
  57. - return true;
  58. -}
  59. -
  60. /* Integer Scalar Move Instruction */
  61. static void store_element(TCGv_i64 val, TCGv_ptr base,
  62. --
  63. 2.33.1