jh8100_jrc.cfg 1.3 KB

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  1. jtag newtap CHIP jrc -irlen 4 -expected-id 0x08100cfd -enable
  2. ## E24 enable handler
  3. jtag configure RV32ACFIMUX.cpu -event tap-enable {
  4. irscan CHIP.jrc 0x2 -endstate RUN/IDLE
  5. drscan CHIP.jrc 16 0x4102 -endstate RUN/IDLE
  6. runtest 10
  7. ## Place jrc in bypass
  8. irscan CHIP.jrc 0xF -endstate RUN/IDLE
  9. runtest 10
  10. }
  11. ## E24 disable handler
  12. jtag configure RV32ACFIMUX.cpu -event tap-disable {
  13. irscan CHIP.jrc 0x2 -endstate RUN/IDLE
  14. drscan CHIP.jrc 16 0x4100 -endstate RUN/IDLE
  15. runtest 10
  16. ## Place jrc in bypass
  17. irscan CHIP.jrc 0xF -endstate RUN/IDLE
  18. }
  19. ## BC enable handler
  20. jtag configure RV64ABCDFHIMSU.cpu -event tap-enable {
  21. irscan CHIP.jrc 0x2 -endstate RUN/IDLE
  22. drscan CHIP.jrc 16 0x4402 -endstate RUN/IDLE
  23. runtest 10
  24. ## Place jrc in bypass
  25. irscan CHIP.jrc 0xF -endstate RUN/IDLE
  26. }
  27. ## BC disable handler
  28. jtag configure RV64ABCDFHIMSU.cpu -event tap-disable {
  29. irscan CHIP.jrc 0x2 -endstate RUN/IDLE
  30. drscan CHIP.jrc 16 0x4400 -endstate RUN/IDLE
  31. runtest 10
  32. ## Place jrc in bypass
  33. irscan CHIP.jrc 0xF -endstate RUN/IDLE
  34. }
  35. jtag configure CHIP.jrc -event post-reset "runtest 20"
  36. jtag configure CHIP.jrc -event setup "jtag tapenable RV64ABCDFHIMSU.cpu"
  37. #"jtag tapenable RV64ABCDFHIMSU.cpu; jtag tapenable RV32ACFIMUX.cpu"