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- From 7b4956f76d1f495d8c7b785c97682a36d852d184 Mon Sep 17 00:00:00 2001
- From: "yilun.xie" <yilun.xie@starfivetech.com>
- Date: Thu, 4 Nov 2021 17:26:53 +0800
- Subject: [PATCH 15/15] add builtin orc.b/clmul/clmulr/clmulh
- ---
- gcc/config/riscv/riscv-builtins.c | 10 ++++++++
- gcc/config/riscv/riscv-ftypes.def | 2 ++
- gcc/config/riscv/riscv.md | 40 ++++++++++++++++++++++++++++++-
- 3 files changed, 51 insertions(+), 1 deletion(-)
- diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
- index 97b1480a15e..674e3f6dc04 100644
- --- a/gcc/config/riscv/riscv-builtins.c
- +++ b/gcc/config/riscv/riscv-builtins.c
- @@ -40,6 +40,7 @@ along with GCC; see the file COPYING3. If not see
- /* Macros to create an enumeration identifier for a function prototype. */
- #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
- #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
- +#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
-
- /* Classifies the prototype of a built-in function. */
- enum riscv_function_type {
- @@ -86,6 +87,8 @@ struct riscv_builtin_description {
- };
-
- AVAIL (hard_float, TARGET_HARD_FLOAT)
- +AVAIL (zbb, TARGET_ZBB)
- +AVAIL (zbc, TARGET_ZBC)
-
- /* Construct a riscv_builtin_description from the given arguments.
-
- @@ -119,6 +122,7 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
- /* Argument types. */
- #define RISCV_ATYPE_VOID void_type_node
- #define RISCV_ATYPE_USI unsigned_intSI_type_node
- +#define RISCV_ATYPE_SI intSI_type_node
-
- /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
- their associated RISCV_ATYPEs. */
- @@ -126,8 +130,14 @@ AVAIL (hard_float, TARGET_HARD_FLOAT)
- RISCV_ATYPE_##A
- #define RISCV_FTYPE_ATYPES1(A, B) \
- RISCV_ATYPE_##A, RISCV_ATYPE_##B
- +#define RISCV_FTYPE_ATYPES2(A, B, C) \
- + RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
-
- static const struct riscv_builtin_description riscv_builtins[] = {
- + DIRECT_BUILTIN (orc_b, RISCV_SI_FTYPE_SI, zbb),
- + DIRECT_BUILTIN (clmul, RISCV_SI_FTYPE_SI_SI, zbc),
- + DIRECT_BUILTIN (clmulh, RISCV_SI_FTYPE_SI_SI, zbc),
- + DIRECT_BUILTIN (clmulr, RISCV_SI_FTYPE_SI_SI, zbc),
- DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
- DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
- };
- diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
- index b19b731bdf2..ab7348d1d7d 100644
- --- a/gcc/config/riscv/riscv-ftypes.def
- +++ b/gcc/config/riscv/riscv-ftypes.def
- @@ -28,3 +28,5 @@ along with GCC; see the file COPYING3. If not see
-
- DEF_RISCV_FTYPE (0, (USI))
- DEF_RISCV_FTYPE (1, (VOID, USI))
- +DEF_RISCV_FTYPE (1, (SI, SI))
- +DEF_RISCV_FTYPE (2, (SI, SI, SI))
- \ No newline at end of file
- diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
- index c3687d57047..26003ac5df7 100644
- --- a/gcc/config/riscv/riscv.md
- +++ b/gcc/config/riscv/riscv.md
- @@ -170,7 +170,7 @@
- (define_attr "type"
- "unknown,branch,jump,call,load,fpload,store,fpstore,
- mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
- - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost"
- + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip"
- (cond [(eq_attr "got" "load") (const_string "load")
-
- ;; If a doubleword move uses these expensive instructions,
- @@ -2504,6 +2504,44 @@
- [(set_attr "length" "0")]
- )
-
- +(define_insn "riscv_orc_b"
- + [(set (match_operand:SI 0 "register_operand" "=r")
- + (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
- + "TARGET_ZBB"
- + "orc.b\t%0,%1,%2"
- + [(set_attr "type" "bitmanip")])
- +
- +(define_insn "riscv_rev8"
- + [(set (match_operand:SI 0 "register_operand" "=r")
- + (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
- + "TARGET_ZBB"
- + "rev8\t%0,%1,%2"
- + [(set_attr "type" "bitmanip")])
- +
- +(define_insn "riscv_clmul"
- + [(set (match_operand:SI 0 "register_operand" "=r")
- + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
- + (match_operand:SI 2 "register_operand" "r"))))]
- + "TARGET_ZBC"
- + "clmul\t%0,%1,%2"
- + [(set_attr "type" "bitmanip")])
- +
- +(define_insn "riscv_clmulh"
- + [(set (match_operand:SI 0 "register_operand" "=r")
- + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
- + (match_operand:SI 2 "register_operand" "r"))))]
- + "TARGET_ZBC"
- + "clmulh\t%0,%1,%2"
- + [(set_attr "type" "bitmanip")])
- +
- +(define_insn "riscv_clmulr"
- + [(set (match_operand:SI 0 "register_operand" "=r")
- + (sign_extend:SI (rotate:SI (match_operand:SI 1 "register_operand" "r")
- + (match_operand:SI 2 "register_operand" "r"))))]
- + "TARGET_ZBC"
- + "clmulr\t%0,%1,%2"
- + [(set_attr "type" "bitmanip")])
- +
- ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
- ;; 32-bit target when using -mtune=sifive-7-series. The first sched pass
- ;; runs before register elimination, and we have a non-obvious dependency
- --
- 2.33.1
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