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- From c1eb999a3aed84d42c792280ea2c313d1c6063ca Mon Sep 17 00:00:00 2001
- From: "yilun.xie" <yilun.xie@starfivetech.com>
- Date: Fri, 22 Oct 2021 16:10:16 +0800
- Subject: [PATCH 10/15] Merge B instruction from 0p94 to 1.0
- ---
- gcc/common/config/riscv/riscv-common.c | 28 +++---------
- gcc/config/riscv/bitmanip.md | 62 +++++---------------------
- gcc/config/riscv/riscv-opts.h | 14 +-----
- 3 files changed, 17 insertions(+), 87 deletions(-)
- diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
- index 28475fc76b5..48eb558bcf5 100644
- --- a/gcc/common/config/riscv/riscv-common.c
- +++ b/gcc/common/config/riscv/riscv-common.c
- @@ -53,13 +53,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
- {"b", "zbb"},
- {"b", "zbs"},
- {"b", "zba"},
- - {"b", "zbp"},
- - {"b", "zbe"},
- - {"b", "zbf"},
- {"b", "zbc"},
- - {"b", "zbm"},
- - {"b", "zbr"},
- - {"b", "zbt"},
- {NULL, NULL}
- };
-
- @@ -111,17 +105,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
- {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
- {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
-
- - {"b", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zba", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbb", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbc", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbe", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbf", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbr", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbm", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbs", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbt", ISA_SPEC_CLASS_NONE, 0, 94},
- - {"zbp", ISA_SPEC_CLASS_NONE, 0, 94},
- + {"b", ISA_SPEC_CLASS_NONE, 1, 0},
- + {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
- + {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
- + {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
- + {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
- /* Terminate the list. */
- {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
- };
- @@ -929,13 +917,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
- {"zba", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBA},
- {"zbb", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBB},
- {"zbs", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBS},
- - {"zbp", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBP},
- - {"zbr", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBR},
- - {"zbe", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBE},
- - {"zbf", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBF},
- {"zbc", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBC},
- - {"zbm", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBM},
- - {"zbt", &gcc_options::x_riscv_bitmanip_subext, MASK_ZBT},
- {NULL, NULL, 0}
- };
-
- diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
- index 6653219c3f0..ceb5c89dd47 100644
- --- a/gcc/config/riscv/bitmanip.md
- +++ b/gcc/config/riscv/bitmanip.md
- @@ -69,7 +69,7 @@
- [(set (match_operand:X 0 "register_operand" "=r")
- (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
- (match_operand:X 2 "register_operand" "r")))]
- - "TARGET_ZBB || TARGET_ZBP"
- + "TARGET_ZBB"
- "<insn>n\t%0,%2,%1"
- [(set_attr "type" "bitmanip")])
-
- @@ -77,7 +77,7 @@
- [(set (match_operand:X 0 "register_operand" "=r")
- (not:X (xor:X (match_operand:X 1 "register_operand" "r")
- (match_operand:X 2 "register_operand" "r"))))]
- - "TARGET_ZBB || TARGET_ZBP"
- + "TARGET_ZBB"
- "xnor\t%0,%1,%2"
- [(set_attr "type" "bitmanip")])
-
- @@ -86,7 +86,7 @@
- (define_insn "*zero_extendhi<GPR:mode>2_bitmanip"
- [(set (match_operand:GPR 0 "register_operand" "=r,r")
- (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- - "TARGET_ZBB || TARGET_ZBP"
- + "TARGET_ZBB"
- "@
- zext.h\t%0,%1
- lhu\t%0,%1"
- @@ -301,7 +301,7 @@
- [(set (match_operand:SI 0 "register_operand" "=r")
- (rotatert:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:QI 2 "arith_operand" "rI")))]
- - "TARGET_ZBB || TARGET_ZBP"
- + "TARGET_ZBB"
- { return TARGET_64BIT ? "ror%i2w\t%0,%1,%2" : "ror%i2\t%0,%1,%2"; }
- [(set_attr "type" "bitmanip")])
-
- @@ -309,7 +309,7 @@
- [(set (match_operand:DI 0 "register_operand" "=r")
- (rotatert:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:QI 2 "arith_operand" "rI")))]
- - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
- + "TARGET_64BIT && TARGET_ZBB"
- "ror%i2\t%0,%1,%2"
- [(set_attr "type" "bitmanip")])
-
- @@ -317,7 +317,7 @@
- [(match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "register_operand" "r")]
- - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
- + "TARGET_64BIT && TARGET_ZBB"
- {
- emit_insn (gen_rotlsi3 (operands[0], operands[1], operands[2]));
- DONE;
- @@ -327,7 +327,7 @@
- [(set (match_operand:SI 0 "register_operand" "=r")
- (rotate:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:QI 2 "register_operand" "r")))]
- - "TARGET_ZBB || TARGET_ZBP"
- + "TARGET_ZBB"
- { return TARGET_64BIT ? "rolw\t%0,%1,%2" : "rol\t%0,%1,%2"; }
- [(set_attr "type" "bitmanip")])
-
- @@ -335,7 +335,7 @@
- [(set (match_operand:DI 0 "register_operand" "=r")
- (rotate:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:QI 2 "register_operand" "r")))]
- - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
- + "TARGET_64BIT && TARGET_ZBB"
- "rol\t%0,%1,%2"
- [(set_attr "type" "bitmanip")])
-
- @@ -343,7 +343,7 @@
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:QI 2 "register_operand" "r"))))]
- - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
- + "TARGET_64BIT && TARGET_ZBB"
- "rolw\t%0,%1,%2"
- [(set_attr "type" "bitmanip")])
-
- @@ -352,7 +352,7 @@
- (define_insn "bswapsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
- - "TARGET_ZBB || TARGET_ZBP"
- + "TARGET_ZBB"
- {
- if (TARGET_64BIT)
- return TARGET_ZBB ? "rev8\t%0,%1\n\tsrai\t%0,%0,32" : "rev8.w\t%0,%1";
- @@ -364,7 +364,7 @@
- (define_insn "bswapdi2"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (bswap:DI (match_operand:DI 1 "register_operand" "r")))]
- - "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBP)"
- + "TARGET_64BIT && TARGET_ZBB"
- "rev8\t%0,%1"
- [(set_attr "type" "bitmanip")])
-
- @@ -378,50 +378,10 @@
-
- ;;; ??? bmat
-
- -(define_insn "*cmix"
- - [(set (match_operand:X 0 "register_operand" "=r")
- - (xor:X (and:X (xor:X (match_operand:X 1 "register_operand" "r")
- - (match_operand:X 3 "register_operand" "r"))
- - (match_operand:X 2 "register_operand" "r"))
- - (match_dup 3)))]
- - "TARGET_ZBT"
- - "cmix\t%0,%2,%1,%3"
- - [(set_attr "type" "bitmanip")])
- -
- ;; ??? Can we do this by using the % communtative constraint?
-
- -(define_insn "*cmix2"
- - [(set (match_operand:X 0 "register_operand" "=r")
- - (xor:X (and:X (xor:X (match_operand:X 1 "register_operand" "r")
- - (match_operand:X 3 "register_operand" "r"))
- - (match_operand:X 2 "register_operand" "r"))
- - (match_dup 1)))]
- - "TARGET_ZBT"
- - "cmix\t%0,%2,%3,%1"
- - [(set_attr "type" "bitmanip")])
- -
- ;;; ??? cmov
-
- -(define_insn "*mov<X:mode>cc_ne_bitmanip"
- - [(set (match_operand:X 0 "register_operand" "=r")
- - (if_then_else:X
- - (ne (match_operand:X 1 "register_operand" "r") (const_int 0))
- - (match_operand:X 2 "register_operand" "r")
- - (match_operand:X 3 "register_operand" "r")))]
- - "TARGET_ZBT"
- - "cmov\t%0,%1,%2,%3"
- - [(set_attr "type" "bitmanip")])
- -
- -(define_insn "*mov<X:mode>cc_eq_bitmanip"
- - [(set (match_operand:X 0 "register_operand" "=r")
- - (if_then_else:X
- - (eq (match_operand:X 1 "register_operand" "r") (const_int 0))
- - (match_operand:X 2 "register_operand" "r")
- - (match_operand:X 3 "register_operand" "r")))]
- - "TARGET_ZBT"
- - "cmov\t%0,%1,%3,%2"
- - [(set_attr "type" "bitmanip")])
- -
- ;;; ??? fs[lr]
-
- (define_insn "*shNadd"
- diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
- index ca3190b6414..61d1e9d96d8 100644
- --- a/gcc/config/riscv/riscv-opts.h
- +++ b/gcc/config/riscv/riscv-opts.h
- @@ -70,24 +70,12 @@ enum stack_protector_guard {
- #define MASK_ZBA (1 << 0)
- #define MASK_ZBB (1 << 1)
- #define MASK_ZBS (1 << 2)
- -#define MASK_ZBP (1 << 3)
- -#define MASK_ZBE (1 << 4)
- -#define MASK_ZBF (1 << 5)
- -#define MASK_ZBC (1 << 6)
- -#define MASK_ZBR (1 << 7)
- -#define MASK_ZBM (1 << 8)
- -#define MASK_ZBT (1 << 9)
- +#define MASK_ZBC (1 << 3)
-
- #define TARGET_ZBA ((riscv_bitmanip_subext & MASK_ZBA) != 0)
- #define TARGET_ZBB ((riscv_bitmanip_subext & MASK_ZBB) != 0)
- #define TARGET_ZBS ((riscv_bitmanip_subext & MASK_ZBS) != 0)
- -#define TARGET_ZBP ((riscv_bitmanip_subext & MASK_ZBP) != 0)
- -#define TARGET_ZBE ((riscv_bitmanip_subext & MASK_ZBE) != 0)
- -#define TARGET_ZBF ((riscv_bitmanip_subext & MASK_ZBF) != 0)
- #define TARGET_ZBC ((riscv_bitmanip_subext & MASK_ZBC) != 0)
- -#define TARGET_ZBR ((riscv_bitmanip_subext & MASK_ZBR) != 0)
- -#define TARGET_ZBM ((riscv_bitmanip_subext & MASK_ZBM) != 0)
- -#define TARGET_ZBT ((riscv_bitmanip_subext & MASK_ZBT) != 0)
-
- #define MASK_ZICSR (1 << 0)
- #define MASK_ZIFENCEI (1 << 1)
- --
- 2.33.1
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