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- From 27272da7ecdf798fbb11d3b6205661a3be55d71f Mon Sep 17 00:00:00 2001
- From: "max.ma" <max.ma@starfivetech.com>
- Date: Wed, 27 Oct 2021 23:50:06 -0700
- Subject: [PATCH 08/11] add cache prefetch instruction
- ---
- gas/config/tc-riscv.c | 42 ++++++++++++++++++++++++++++++++++++++
- include/opcode/riscv-opc.h | 1 +
- include/opcode/riscv.h | 9 ++++++++
- opcodes/riscv-dis.c | 8 ++++++++
- opcodes/riscv-opc.c | 1 +
- 5 files changed, 61 insertions(+)
- diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
- index 4aaba3c403..3df6b6c0f6 100644
- --- a/gas/config/tc-riscv.c
- +++ b/gas/config/tc-riscv.c
- @@ -1116,6 +1116,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
- case ')': break;
- case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
- case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
- + case '#': used_bits |= ENCODE_PREF_TIMM (-1U); break;
- + case '+': used_bits |= ENCODE_PREF_SIMM (-1U); break;
- case 'A': break; /* Macro operand, must be symbol. */
- case 'B': break; /* Macro operand, must be symbol or constant. */
- case 'I': break; /* Macro operand, must be constant. */
- @@ -1542,6 +1544,27 @@ check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex,
- normalize_constant_expr (ex);
- }
-
- +/* The pref type should be one of the following:
- + 0000 - scalar prefetch L1, fetch data as if for a normal scalar load,
- + and imply load into all lower cache destination levels.
- + 0001 - scalar prefetch L2, fetch data and place the cache-line into L2,
- + and imply load into all lower cache destination levels.
- + 0010 - scalar prefetch L3, fetch data and place the cache-line into L3,
- + and imply load into all lower cache destination levels.
- + 0011 - scalar prefetch L4, fetch data and place the cache-line into L4,
- + and imply load into all lower cache destination levels
- + (if the L5 is in the cache heirarchy).
- + 1000 - vector prefetch L1, fetch data as if for a normal scalar load
- + but place the cache-line into vector buffer (vector L1) ,
- + and imply load into all lower cache destination levels.
- +*/
- +
- +static bfd_boolean check_pref_type(unsigned long type)
- +{
- + if (type != 0 && type != 1 && type != 3 && type != 8)
- + as_bad (_("Improper pref type (%lu)"), type);
- +}
- +
- static symbolS *
- make_internal_label (void)
- {
- @@ -2655,6 +2678,25 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
- s = expr_end;
- continue;
-
- + case '#':
- + my_getExpression (imm_expr, s);
- + check_pref_type((unsigned long)imm_expr->X_add_number);
- + INSERT_OPERAND (PREF_TYPE, *ip, imm_expr->X_add_number);
- + imm_expr->X_op = O_absent;
- + s = expr_end;
- + continue;
- +
- + case '+':
- + my_getExpression (imm_expr, s);
- + check_absolute_expr (ip, imm_expr, FALSE);
- + if ((unsigned long) imm_expr->X_add_number > 0xff)
- + as_bad (_("Improper pref offset value (%lu)"),
- + (unsigned long) imm_expr->X_add_number);
- + INSERT_OPERAND (PREF_OFFSET, *ip, imm_expr->X_add_number);
- + imm_expr->X_op = O_absent;
- + s = expr_end;
- + continue;
- +
- case 'E': /* Control register. */
- insn_with_csr = true;
- explicit_priv_attr = true;
- diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
- index 566ab6e706..917000844b 100644
- --- a/include/opcode/riscv-opc.h
- +++ b/include/opcode/riscv-opc.h
- @@ -276,6 +276,7 @@
- #define MASK_CFLUSH_D_L2 0xfff07fff
- #define MATCH_CDISCARD_D_L2 0xfc600073
- #define MASK_CDISCARD_D_L2 0xfff07fff
- +#define MASK_PREF 0x7fff
- #define MATCH_CSRRW 0x1073
- #define MASK_CSRRW 0x707f
- #define MATCH_CSRRS 0x2073
- diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
- index 92b7ed18f9..52f653c288 100644
- --- a/include/opcode/riscv.h
- +++ b/include/opcode/riscv.h
- @@ -178,6 +178,11 @@ static const char * const riscv_vma[2] =
- (RV_X(x, 0, 10) << 20)
- #define ENCODE_RVV_VC_IMM(x) \
- (RV_X(x, 0, 11) << 20)
- +#define ENCODE_PREF_TIMM(x) \
- + (RV_X(x, 0, 4) << 20)
- +#define ENCODE_PREF_SIMM(x) \
- + (RV_X(x, 0, 8) << 24)
- +
-
- #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
- #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
- @@ -277,6 +282,10 @@ static const char * const riscv_vma[2] =
- #define OP_SH_FUNCT7 25
- #define OP_MASK_FUNCT2 0x3
- #define OP_SH_FUNCT2 25
- +#define OP_MASK_PREF_TYPE 0x0f
- +#define OP_SH_PREF_TYPE 20
- +#define OP_MASK_PREF_OFFSET 0xff
- +#define OP_SH_PREF_OFFSET 24
-
- /* RVC fields. */
-
- diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
- index a36756cb4c..cd88483ed8 100644
- --- a/opcodes/riscv-dis.c
- +++ b/opcodes/riscv-dis.c
- @@ -356,6 +356,14 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
- print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
- break;
-
- + case '#':
- + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (PREF_TYPE, l));
- + break;
- +
- + case '+':
- + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (PREF_OFFSET, l));
- + break;
- +
- case 'S':
- case 'U':
- print (info->stream, "%s", riscv_fpr_names[rs1]);
- diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
- index ea0fa1209c..ed7bee8416 100644
- --- a/opcodes/riscv-opc.c
- +++ b/opcodes/riscv-opc.c
- @@ -759,6 +759,7 @@ const struct riscv_opcode riscv_opcodes[] =
- {"snez", 0, INSN_CLASS_I, "d,t", MATCH_SLTU, MASK_SLTU|MASK_RS1, match_opcode, INSN_ALIAS },
- {"sltz", 0, INSN_CLASS_I, "d,s", MATCH_SLT, MASK_SLT|MASK_RS2, match_opcode, INSN_ALIAS },
- {"sgtz", 0, INSN_CLASS_I, "d,t", MATCH_SLT, MASK_SLT|MASK_RS1, match_opcode, INSN_ALIAS },
- +{"pref", 0, INSN_CLASS_I, "#,+(s)", MATCH_SLTI, MASK_PREF, match_opcode, INSN_ALIAS },
- {"slti", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
- {"slt", 0, INSN_CLASS_I, "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 },
- {"slt", 0, INSN_CLASS_I, "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
- --
- 2.33.1
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