0002-update-B-instruction-to-1.0-and-Merge-four-Custom-CS.patch 65 KB

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  1. From 05cd9526d2438fab6b4b671d682445aae38b5438 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Fri, 29 Oct 2021 10:16:06 +0800
  4. Subject: [PATCH 2/3] update B instruction to 1.0 and Merge four Custom CSR
  5. cache instruction
  6. ---
  7. clang/include/clang/Basic/BuiltinsRISCV.def | 33 --
  8. clang/lib/CodeGen/CGBuiltin.cpp | 92 +---
  9. clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 3 +-
  10. llvm/include/llvm/IR/IntrinsicsRISCV.td | 23 -
  11. .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 30 --
  12. .../MCTargetDesc/RISCVTargetStreamer.cpp | 12 -
  13. llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 323 +-----------
  14. llvm/lib/Target/RISCV/RISCVInstrFormats.td | 12 +
  15. llvm/lib/Target/RISCV/RISCVInstrInfo.td | 13 +
  16. llvm/lib/Target/RISCV/RISCVInstrInfoB.td | 473 ++----------------
  17. 10 files changed, 68 insertions(+), 946 deletions(-)
  18. diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def b/clang/include/clang/Basic/BuiltinsRISCV.def
  19. index b2b4950f92bd..583c5712e41d 100644
  20. --- a/clang/include/clang/Basic/BuiltinsRISCV.def
  21. +++ b/clang/include/clang/Basic/BuiltinsRISCV.def
  22. @@ -26,38 +26,5 @@ TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "experimental-zbc")
  23. TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "experimental-zbc")
  24. TARGET_BUILTIN(__builtin_riscv_clmulr, "LiLiLi", "nc", "experimental-zbc")
  25. -// Zbe extension
  26. -TARGET_BUILTIN(__builtin_riscv_bcompress_32, "ZiZiZi", "nc", "experimental-zbe")
  27. -TARGET_BUILTIN(__builtin_riscv_bcompress_64, "WiWiWi", "nc",
  28. - "experimental-zbe,64bit")
  29. -TARGET_BUILTIN(__builtin_riscv_bdecompress_32, "ZiZiZi", "nc",
  30. - "experimental-zbe")
  31. -TARGET_BUILTIN(__builtin_riscv_bdecompress_64, "WiWiWi", "nc",
  32. - "experimental-zbe,64bit")
  33. -
  34. -// Zbp extension
  35. -TARGET_BUILTIN(__builtin_riscv_grev_32, "ZiZiZi", "nc", "experimental-zbp")
  36. -TARGET_BUILTIN(__builtin_riscv_grev_64, "WiWiWi", "nc", "experimental-zbp,64bit")
  37. -TARGET_BUILTIN(__builtin_riscv_gorc_32, "ZiZiZi", "nc", "experimental-zbp")
  38. -TARGET_BUILTIN(__builtin_riscv_gorc_64, "WiWiWi", "nc", "experimental-zbp,64bit")
  39. -TARGET_BUILTIN(__builtin_riscv_shfl_32, "ZiZiZi", "nc", "experimental-zbp")
  40. -TARGET_BUILTIN(__builtin_riscv_shfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
  41. -TARGET_BUILTIN(__builtin_riscv_unshfl_32, "ZiZiZi", "nc", "experimental-zbp")
  42. -TARGET_BUILTIN(__builtin_riscv_unshfl_64, "WiWiWi", "nc", "experimental-zbp,64bit")
  43. -TARGET_BUILTIN(__builtin_riscv_xperm_n, "LiLiLi", "nc", "experimental-zbp")
  44. -TARGET_BUILTIN(__builtin_riscv_xperm_b, "LiLiLi", "nc", "experimental-zbp")
  45. -TARGET_BUILTIN(__builtin_riscv_xperm_h, "LiLiLi", "nc", "experimental-zbp")
  46. -TARGET_BUILTIN(__builtin_riscv_xperm_w, "WiWiWi", "nc", "experimental-zbp,64bit")
  47. -
  48. -// Zbr extension
  49. -TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
  50. -TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
  51. -TARGET_BUILTIN(__builtin_riscv_crc32_w, "LiLi", "nc", "experimental-zbr")
  52. -TARGET_BUILTIN(__builtin_riscv_crc32c_b, "LiLi", "nc", "experimental-zbr")
  53. -TARGET_BUILTIN(__builtin_riscv_crc32c_h, "LiLi", "nc", "experimental-zbr")
  54. -TARGET_BUILTIN(__builtin_riscv_crc32c_w, "LiLi", "nc", "experimental-zbr")
  55. -TARGET_BUILTIN(__builtin_riscv_crc32_d, "LiLi", "nc", "experimental-zbr")
  56. -TARGET_BUILTIN(__builtin_riscv_crc32c_d, "LiLi", "nc", "experimental-zbr")
  57. -
  58. #undef BUILTIN
  59. #undef TARGET_BUILTIN
  60. diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
  61. index 2a9ab387fa52..b38c8bf7d383 100644
  62. --- a/clang/lib/CodeGen/CGBuiltin.cpp
  63. +++ b/clang/lib/CodeGen/CGBuiltin.cpp
  64. @@ -18514,31 +18514,7 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
  65. case RISCV::BI__builtin_riscv_orc_b_64:
  66. case RISCV::BI__builtin_riscv_clmul:
  67. case RISCV::BI__builtin_riscv_clmulh:
  68. - case RISCV::BI__builtin_riscv_clmulr:
  69. - case RISCV::BI__builtin_riscv_bcompress_32:
  70. - case RISCV::BI__builtin_riscv_bcompress_64:
  71. - case RISCV::BI__builtin_riscv_bdecompress_32:
  72. - case RISCV::BI__builtin_riscv_bdecompress_64:
  73. - case RISCV::BI__builtin_riscv_grev_32:
  74. - case RISCV::BI__builtin_riscv_grev_64:
  75. - case RISCV::BI__builtin_riscv_gorc_32:
  76. - case RISCV::BI__builtin_riscv_gorc_64:
  77. - case RISCV::BI__builtin_riscv_shfl_32:
  78. - case RISCV::BI__builtin_riscv_shfl_64:
  79. - case RISCV::BI__builtin_riscv_unshfl_32:
  80. - case RISCV::BI__builtin_riscv_unshfl_64:
  81. - case RISCV::BI__builtin_riscv_xperm_n:
  82. - case RISCV::BI__builtin_riscv_xperm_b:
  83. - case RISCV::BI__builtin_riscv_xperm_h:
  84. - case RISCV::BI__builtin_riscv_xperm_w:
  85. - case RISCV::BI__builtin_riscv_crc32_b:
  86. - case RISCV::BI__builtin_riscv_crc32_h:
  87. - case RISCV::BI__builtin_riscv_crc32_w:
  88. - case RISCV::BI__builtin_riscv_crc32_d:
  89. - case RISCV::BI__builtin_riscv_crc32c_b:
  90. - case RISCV::BI__builtin_riscv_crc32c_h:
  91. - case RISCV::BI__builtin_riscv_crc32c_w:
  92. - case RISCV::BI__builtin_riscv_crc32c_d: {
  93. + case RISCV::BI__builtin_riscv_clmulr: {
  94. switch (BuiltinID) {
  95. default: llvm_unreachable("unexpected builtin ID");
  96. // Zbb
  97. @@ -18557,72 +18533,6 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
  98. case RISCV::BI__builtin_riscv_clmulr:
  99. ID = Intrinsic::riscv_clmulr;
  100. break;
  101. -
  102. - // Zbe
  103. - case RISCV::BI__builtin_riscv_bcompress_32:
  104. - case RISCV::BI__builtin_riscv_bcompress_64:
  105. - ID = Intrinsic::riscv_bcompress;
  106. - break;
  107. - case RISCV::BI__builtin_riscv_bdecompress_32:
  108. - case RISCV::BI__builtin_riscv_bdecompress_64:
  109. - ID = Intrinsic::riscv_bdecompress;
  110. - break;
  111. -
  112. - // Zbp
  113. - case RISCV::BI__builtin_riscv_grev_32:
  114. - case RISCV::BI__builtin_riscv_grev_64:
  115. - ID = Intrinsic::riscv_grev;
  116. - break;
  117. - case RISCV::BI__builtin_riscv_gorc_32:
  118. - case RISCV::BI__builtin_riscv_gorc_64:
  119. - ID = Intrinsic::riscv_gorc;
  120. - break;
  121. - case RISCV::BI__builtin_riscv_shfl_32:
  122. - case RISCV::BI__builtin_riscv_shfl_64:
  123. - ID = Intrinsic::riscv_shfl;
  124. - break;
  125. - case RISCV::BI__builtin_riscv_unshfl_32:
  126. - case RISCV::BI__builtin_riscv_unshfl_64:
  127. - ID = Intrinsic::riscv_unshfl;
  128. - break;
  129. - case RISCV::BI__builtin_riscv_xperm_n:
  130. - ID = Intrinsic::riscv_xperm_n;
  131. - break;
  132. - case RISCV::BI__builtin_riscv_xperm_b:
  133. - ID = Intrinsic::riscv_xperm_b;
  134. - break;
  135. - case RISCV::BI__builtin_riscv_xperm_h:
  136. - ID = Intrinsic::riscv_xperm_h;
  137. - break;
  138. - case RISCV::BI__builtin_riscv_xperm_w:
  139. - ID = Intrinsic::riscv_xperm_w;
  140. - break;
  141. -
  142. - // Zbr
  143. - case RISCV::BI__builtin_riscv_crc32_b:
  144. - ID = Intrinsic::riscv_crc32_b;
  145. - break;
  146. - case RISCV::BI__builtin_riscv_crc32_h:
  147. - ID = Intrinsic::riscv_crc32_h;
  148. - break;
  149. - case RISCV::BI__builtin_riscv_crc32_w:
  150. - ID = Intrinsic::riscv_crc32_w;
  151. - break;
  152. - case RISCV::BI__builtin_riscv_crc32_d:
  153. - ID = Intrinsic::riscv_crc32_d;
  154. - break;
  155. - case RISCV::BI__builtin_riscv_crc32c_b:
  156. - ID = Intrinsic::riscv_crc32c_b;
  157. - break;
  158. - case RISCV::BI__builtin_riscv_crc32c_h:
  159. - ID = Intrinsic::riscv_crc32c_h;
  160. - break;
  161. - case RISCV::BI__builtin_riscv_crc32c_w:
  162. - ID = Intrinsic::riscv_crc32c_w;
  163. - break;
  164. - case RISCV::BI__builtin_riscv_crc32c_d:
  165. - ID = Intrinsic::riscv_crc32c_d;
  166. - break;
  167. }
  168. IntrinsicTypes = {ResultType};
  169. diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  170. index f54ac5b166d4..e7ac0a6a0e14 100644
  171. --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  172. +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  173. @@ -61,8 +61,7 @@ isExperimentalExtension(StringRef Ext) {
  174. if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
  175. Ext == "zbs")
  176. return RISCVExtensionVersion{"1", "0"};
  177. - if (Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
  178. - Ext == "zbr" || Ext == "zbt" || Ext == "zbproposedc")
  179. + if (Ext == "zbproposedc")
  180. return RISCVExtensionVersion{"0", "94"};
  181. if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
  182. return RISCVExtensionVersion{"0", "10"};
  183. diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
  184. index b3f82c7022a8..053f98452652 100644
  185. --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
  186. +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
  187. @@ -89,29 +89,6 @@ let TargetPrefix = "riscv" in {
  188. def int_riscv_clmulh : BitManipGPRGPRIntrinsics;
  189. def int_riscv_clmulr : BitManipGPRGPRIntrinsics;
  190. - // Zbe
  191. - def int_riscv_bcompress : BitManipGPRGPRIntrinsics;
  192. - def int_riscv_bdecompress : BitManipGPRGPRIntrinsics;
  193. -
  194. - // Zbp
  195. - def int_riscv_grev : BitManipGPRGPRIntrinsics;
  196. - def int_riscv_gorc : BitManipGPRGPRIntrinsics;
  197. - def int_riscv_shfl : BitManipGPRGPRIntrinsics;
  198. - def int_riscv_unshfl : BitManipGPRGPRIntrinsics;
  199. - def int_riscv_xperm_n : BitManipGPRGPRIntrinsics;
  200. - def int_riscv_xperm_b : BitManipGPRGPRIntrinsics;
  201. - def int_riscv_xperm_h : BitManipGPRGPRIntrinsics;
  202. - def int_riscv_xperm_w : BitManipGPRGPRIntrinsics;
  203. -
  204. - // Zbr
  205. - def int_riscv_crc32_b : BitManipGPRIntrinsics;
  206. - def int_riscv_crc32_h : BitManipGPRIntrinsics;
  207. - def int_riscv_crc32_w : BitManipGPRIntrinsics;
  208. - def int_riscv_crc32_d : BitManipGPRIntrinsics;
  209. - def int_riscv_crc32c_b : BitManipGPRIntrinsics;
  210. - def int_riscv_crc32c_h : BitManipGPRIntrinsics;
  211. - def int_riscv_crc32c_w : BitManipGPRIntrinsics;
  212. - def int_riscv_crc32c_d : BitManipGPRIntrinsics;
  213. } // TargetPrefix = "riscv"
  214. //===----------------------------------------------------------------------===//
  215. diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  216. index 17548b7141a3..14e67bb8c6c9 100644
  217. --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  218. +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  219. @@ -2078,15 +2078,9 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
  220. clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
  221. clearFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
  222. clearFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
  223. - clearFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
  224. - clearFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
  225. - clearFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
  226. - clearFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
  227. clearFeatureBits(RISCV::FeatureStdExtZbproposedc,
  228. "experimental-zbproposedc");
  229. - clearFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
  230. clearFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
  231. - clearFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
  232. clearFeatureBits(RISCV::FeatureStdExtZvamo, "experimental-zvamo");
  233. clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
  234. @@ -2126,23 +2120,11 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
  235. setFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
  236. else if (Ext == "zbc")
  237. setFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
  238. - else if (Ext == "zbe")
  239. - setFeatureBits(RISCV::FeatureStdExtZbe, "experimental-zbe");
  240. - else if (Ext == "zbf")
  241. - setFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
  242. - else if (Ext == "zbm")
  243. - setFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
  244. - else if (Ext == "zbp")
  245. - setFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
  246. else if (Ext == "zbproposedc")
  247. setFeatureBits(RISCV::FeatureStdExtZbproposedc,
  248. "experimental-zbproposedc");
  249. - else if (Ext == "zbr")
  250. - setFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
  251. else if (Ext == "zbs")
  252. setFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
  253. - else if (Ext == "zbt")
  254. - setFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
  255. else if (Ext == "zfh")
  256. setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
  257. else if (Ext == "zvamo")
  258. @@ -2203,22 +2185,10 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
  259. formalArchStr = (Twine(formalArchStr) + "_zbb1p0").str();
  260. if (getFeatureBits(RISCV::FeatureStdExtZbc))
  261. formalArchStr = (Twine(formalArchStr) + "_zbc1p0").str();
  262. - if (getFeatureBits(RISCV::FeatureStdExtZbe))
  263. - formalArchStr = (Twine(formalArchStr) + "_zbe0p94").str();
  264. - if (getFeatureBits(RISCV::FeatureStdExtZbf))
  265. - formalArchStr = (Twine(formalArchStr) + "_zbf0p94").str();
  266. - if (getFeatureBits(RISCV::FeatureStdExtZbm))
  267. - formalArchStr = (Twine(formalArchStr) + "_zbm0p94").str();
  268. - if (getFeatureBits(RISCV::FeatureStdExtZbp))
  269. - formalArchStr = (Twine(formalArchStr) + "_zbp0p94").str();
  270. if (getFeatureBits(RISCV::FeatureStdExtZbproposedc))
  271. formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p94").str();
  272. - if (getFeatureBits(RISCV::FeatureStdExtZbr))
  273. - formalArchStr = (Twine(formalArchStr) + "_zbr0p94").str();
  274. if (getFeatureBits(RISCV::FeatureStdExtZbs))
  275. formalArchStr = (Twine(formalArchStr) + "_zbs1p0").str();
  276. - if (getFeatureBits(RISCV::FeatureStdExtZbt))
  277. - formalArchStr = (Twine(formalArchStr) + "_zbt0p94").str();
  278. if (getFeatureBits(RISCV::FeatureStdExtZvamo))
  279. formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();
  280. if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
  281. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  282. index 14b54fb83097..043fb2b8c962 100644
  283. --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  284. +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  285. @@ -72,22 +72,10 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
  286. Arch += "_zbb1p0";
  287. if (STI.hasFeature(RISCV::FeatureStdExtZbc))
  288. Arch += "_zbc1p0";
  289. - if (STI.hasFeature(RISCV::FeatureStdExtZbe))
  290. - Arch += "_zbe0p94";
  291. - if (STI.hasFeature(RISCV::FeatureStdExtZbf))
  292. - Arch += "_zbf0p94";
  293. - if (STI.hasFeature(RISCV::FeatureStdExtZbm))
  294. - Arch += "_zbm0p94";
  295. - if (STI.hasFeature(RISCV::FeatureStdExtZbp))
  296. - Arch += "_zbp0p94";
  297. if (STI.hasFeature(RISCV::FeatureStdExtZbproposedc))
  298. Arch += "_zbproposedc0p94";
  299. - if (STI.hasFeature(RISCV::FeatureStdExtZbr))
  300. - Arch += "_zbr0p94";
  301. if (STI.hasFeature(RISCV::FeatureStdExtZbs))
  302. Arch += "_zbs1p0";
  303. - if (STI.hasFeature(RISCV::FeatureStdExtZbt))
  304. - Arch += "_zbt0p94";
  305. if (STI.hasFeature(RISCV::FeatureStdExtZvamo))
  306. Arch += "_zvamo0p10";
  307. if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
  308. diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  309. index 005f653975dd..55b592ecec58 100644
  310. --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  311. +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  312. @@ -245,7 +245,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
  313. setOperationAction(ISD::SRL_PARTS, XLenVT, Custom);
  314. setOperationAction(ISD::SRA_PARTS, XLenVT, Custom);
  315. - if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) {
  316. + if (Subtarget.hasStdExtZbb()) {
  317. if (Subtarget.is64Bit()) {
  318. setOperationAction(ISD::ROTL, MVT::i32, Custom);
  319. setOperationAction(ISD::ROTR, MVT::i32, Custom);
  320. @@ -255,26 +255,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
  321. setOperationAction(ISD::ROTR, XLenVT, Expand);
  322. }
  323. - if (Subtarget.hasStdExtZbp()) {
  324. - // Custom lower bswap/bitreverse so we can convert them to GREVI to enable
  325. - // more combining.
  326. - setOperationAction(ISD::BITREVERSE, XLenVT, Custom);
  327. - setOperationAction(ISD::BSWAP, XLenVT, Custom);
  328. - setOperationAction(ISD::BITREVERSE, MVT::i8, Custom);
  329. - // BSWAP i8 doesn't exist.
  330. - setOperationAction(ISD::BITREVERSE, MVT::i16, Custom);
  331. - setOperationAction(ISD::BSWAP, MVT::i16, Custom);
  332. -
  333. - if (Subtarget.is64Bit()) {
  334. - setOperationAction(ISD::BITREVERSE, MVT::i32, Custom);
  335. - setOperationAction(ISD::BSWAP, MVT::i32, Custom);
  336. - }
  337. - } else {
  338. - // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
  339. - // pattern match it directly in isel.
  340. - setOperationAction(ISD::BSWAP, XLenVT,
  341. - Subtarget.hasStdExtZbb() ? Legal : Expand);
  342. - }
  343. + // With Zbb we have an XLen rev8 instruction, but not GREVI. So we'll
  344. + // pattern match it directly in isel.
  345. + setOperationAction(ISD::BSWAP, XLenVT,
  346. + Subtarget.hasStdExtZbb() ? Legal : Expand);
  347. if (Subtarget.hasStdExtZbb()) {
  348. setOperationAction(ISD::SMIN, XLenVT, Legal);
  349. @@ -294,18 +278,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
  350. setOperationAction(ISD::CTPOP, XLenVT, Expand);
  351. }
  352. - if (Subtarget.hasStdExtZbt()) {
  353. - setOperationAction(ISD::FSHL, XLenVT, Custom);
  354. - setOperationAction(ISD::FSHR, XLenVT, Custom);
  355. - setOperationAction(ISD::SELECT, XLenVT, Legal);
  356. -
  357. - if (Subtarget.is64Bit()) {
  358. - setOperationAction(ISD::FSHL, MVT::i32, Custom);
  359. - setOperationAction(ISD::FSHR, MVT::i32, Custom);
  360. - }
  361. - } else {
  362. - setOperationAction(ISD::SELECT, XLenVT, Custom);
  363. - }
  364. + setOperationAction(ISD::SELECT, XLenVT, Custom);
  365. +
  366. static const ISD::CondCode FPCCToExpand[] = {
  367. ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
  368. @@ -2416,20 +2390,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
  369. return LowerINTRINSIC_W_CHAIN(Op, DAG);
  370. case ISD::INTRINSIC_VOID:
  371. return LowerINTRINSIC_VOID(Op, DAG);
  372. - case ISD::BSWAP:
  373. - case ISD::BITREVERSE: {
  374. - // Convert BSWAP/BITREVERSE to GREVI to enable GREVI combinining.
  375. - assert(Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
  376. - MVT VT = Op.getSimpleValueType();
  377. - SDLoc DL(Op);
  378. - // Start with the maximum immediate value which is the bitwidth - 1.
  379. - unsigned Imm = VT.getSizeInBits() - 1;
  380. - // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
  381. - if (Op.getOpcode() == ISD::BSWAP)
  382. - Imm &= ~0x7U;
  383. - return DAG.getNode(RISCVISD::GREV, DL, VT, Op.getOperand(0),
  384. - DAG.getConstant(Imm, DL, VT));
  385. - }
  386. case ISD::FSHL:
  387. case ISD::FSHR: {
  388. MVT VT = Op.getSimpleValueType();
  389. @@ -3841,24 +3801,6 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
  390. // Lower to the GORCI encoding for orc.b.
  391. return DAG.getNode(RISCVISD::GORC, DL, XLenVT, Op.getOperand(1),
  392. DAG.getConstant(7, DL, XLenVT));
  393. - case Intrinsic::riscv_grev:
  394. - case Intrinsic::riscv_gorc: {
  395. - unsigned Opc =
  396. - IntNo == Intrinsic::riscv_grev ? RISCVISD::GREV : RISCVISD::GORC;
  397. - return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
  398. - }
  399. - case Intrinsic::riscv_shfl:
  400. - case Intrinsic::riscv_unshfl: {
  401. - unsigned Opc =
  402. - IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
  403. - return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
  404. - }
  405. - case Intrinsic::riscv_bcompress:
  406. - case Intrinsic::riscv_bdecompress: {
  407. - unsigned Opc = IntNo == Intrinsic::riscv_bcompress ? RISCVISD::BCOMPRESS
  408. - : RISCVISD::BDECOMPRESS;
  409. - return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1), Op.getOperand(2));
  410. - }
  411. case Intrinsic::riscv_vmv_x_s:
  412. assert(Op.getValueType() == XLenVT && "Unexpected VT!");
  413. return DAG.getNode(RISCVISD::VMV_X_S, DL, Op.getValueType(),
  414. @@ -5712,26 +5654,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
  415. Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes));
  416. break;
  417. }
  418. - case ISD::BSWAP:
  419. - case ISD::BITREVERSE: {
  420. - MVT VT = N->getSimpleValueType(0);
  421. - MVT XLenVT = Subtarget.getXLenVT();
  422. - assert((VT == MVT::i8 || VT == MVT::i16 ||
  423. - (VT == MVT::i32 && Subtarget.is64Bit())) &&
  424. - Subtarget.hasStdExtZbp() && "Unexpected custom legalisation");
  425. - SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, N->getOperand(0));
  426. - unsigned Imm = VT.getSizeInBits() - 1;
  427. - // If this is BSWAP rather than BITREVERSE, clear the lower 3 bits.
  428. - if (N->getOpcode() == ISD::BSWAP)
  429. - Imm &= ~0x7U;
  430. - unsigned Opc = Subtarget.is64Bit() ? RISCVISD::GREVW : RISCVISD::GREV;
  431. - SDValue GREVI =
  432. - DAG.getNode(Opc, DL, XLenVT, NewOp0, DAG.getConstant(Imm, DL, XLenVT));
  433. - // ReplaceNodeResults requires we maintain the same type for the return
  434. - // value.
  435. - Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, GREVI));
  436. - break;
  437. - }
  438. case ISD::FSHL:
  439. case ISD::FSHR: {
  440. assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
  441. @@ -5816,67 +5738,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
  442. default:
  443. llvm_unreachable(
  444. "Don't know how to custom type legalize this intrinsic!");
  445. - case Intrinsic::riscv_orc_b: {
  446. - // Lower to the GORCI encoding for orc.b with the operand extended.
  447. - SDValue NewOp =
  448. - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
  449. - // If Zbp is enabled, use GORCIW which will sign extend the result.
  450. - unsigned Opc =
  451. - Subtarget.hasStdExtZbp() ? RISCVISD::GORCW : RISCVISD::GORC;
  452. - SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp,
  453. - DAG.getConstant(7, DL, MVT::i64));
  454. - Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
  455. - return;
  456. - }
  457. - case Intrinsic::riscv_grev:
  458. - case Intrinsic::riscv_gorc: {
  459. - assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
  460. - "Unexpected custom legalisation");
  461. - SDValue NewOp1 =
  462. - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
  463. - SDValue NewOp2 =
  464. - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
  465. - unsigned Opc =
  466. - IntNo == Intrinsic::riscv_grev ? RISCVISD::GREVW : RISCVISD::GORCW;
  467. - SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
  468. - Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
  469. - break;
  470. - }
  471. - case Intrinsic::riscv_shfl:
  472. - case Intrinsic::riscv_unshfl: {
  473. - assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
  474. - "Unexpected custom legalisation");
  475. - SDValue NewOp1 =
  476. - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
  477. - SDValue NewOp2 =
  478. - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
  479. - unsigned Opc =
  480. - IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFLW : RISCVISD::UNSHFLW;
  481. - if (isa<ConstantSDNode>(N->getOperand(2))) {
  482. - NewOp2 = DAG.getNode(ISD::AND, DL, MVT::i64, NewOp2,
  483. - DAG.getConstant(0xf, DL, MVT::i64));
  484. - Opc =
  485. - IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL;
  486. - }
  487. - SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
  488. - Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
  489. - break;
  490. - }
  491. - case Intrinsic::riscv_bcompress:
  492. - case Intrinsic::riscv_bdecompress: {
  493. - assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
  494. - "Unexpected custom legalisation");
  495. - SDValue NewOp1 =
  496. - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
  497. - SDValue NewOp2 =
  498. - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
  499. - unsigned Opc = IntNo == Intrinsic::riscv_bcompress
  500. - ? RISCVISD::BCOMPRESSW
  501. - : RISCVISD::BDECOMPRESSW;
  502. - SDValue Res = DAG.getNode(Opc, DL, MVT::i64, NewOp1, NewOp2);
  503. - Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
  504. - break;
  505. - }
  506. case Intrinsic::riscv_vmv_x_s: {
  507. EVT VT = N->getValueType(0);
  508. MVT XLenVT = Subtarget.getXLenVT();
  509. @@ -6060,91 +5921,6 @@ static Optional<RISCVBitmanipPat> matchGREVIPat(SDValue Op) {
  510. return matchRISCVBitmanipPat(Op, BitmanipMasks);
  511. }
  512. -// Match the following pattern as a GREVI(W) operation
  513. -// (or (BITMANIP_SHL x), (BITMANIP_SRL x))
  514. -static SDValue combineORToGREV(SDValue Op, SelectionDAG &DAG,
  515. - const RISCVSubtarget &Subtarget) {
  516. - assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson");
  517. - EVT VT = Op.getValueType();
  518. -
  519. - if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) {
  520. - auto LHS = matchGREVIPat(Op.getOperand(0));
  521. - auto RHS = matchGREVIPat(Op.getOperand(1));
  522. - if (LHS && RHS && LHS->formsPairWith(*RHS)) {
  523. - SDLoc DL(Op);
  524. - return DAG.getNode(RISCVISD::GREV, DL, VT, LHS->Op,
  525. - DAG.getConstant(LHS->ShAmt, DL, VT));
  526. - }
  527. - }
  528. - return SDValue();
  529. -}
  530. -
  531. -// Matches any the following pattern as a GORCI(W) operation
  532. -// 1. (or (GREVI x, shamt), x) if shamt is a power of 2
  533. -// 2. (or x, (GREVI x, shamt)) if shamt is a power of 2
  534. -// 3. (or (or (BITMANIP_SHL x), x), (BITMANIP_SRL x))
  535. -// Note that with the variant of 3.,
  536. -// (or (or (BITMANIP_SHL x), (BITMANIP_SRL x)), x)
  537. -// the inner pattern will first be matched as GREVI and then the outer
  538. -// pattern will be matched to GORC via the first rule above.
  539. -// 4. (or (rotl/rotr x, bitwidth/2), x)
  540. -static SDValue combineORToGORC(SDValue Op, SelectionDAG &DAG,
  541. - const RISCVSubtarget &Subtarget) {
  542. - assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson");
  543. - EVT VT = Op.getValueType();
  544. -
  545. - if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) {
  546. - SDLoc DL(Op);
  547. - SDValue Op0 = Op.getOperand(0);
  548. - SDValue Op1 = Op.getOperand(1);
  549. -
  550. - auto MatchOROfReverse = [&](SDValue Reverse, SDValue X) {
  551. - if (Reverse.getOpcode() == RISCVISD::GREV && Reverse.getOperand(0) == X &&
  552. - isa<ConstantSDNode>(Reverse.getOperand(1)) &&
  553. - isPowerOf2_32(Reverse.getConstantOperandVal(1)))
  554. - return DAG.getNode(RISCVISD::GORC, DL, VT, X, Reverse.getOperand(1));
  555. - // We can also form GORCI from ROTL/ROTR by half the bitwidth.
  556. - if ((Reverse.getOpcode() == ISD::ROTL ||
  557. - Reverse.getOpcode() == ISD::ROTR) &&
  558. - Reverse.getOperand(0) == X &&
  559. - isa<ConstantSDNode>(Reverse.getOperand(1))) {
  560. - uint64_t RotAmt = Reverse.getConstantOperandVal(1);
  561. - if (RotAmt == (VT.getSizeInBits() / 2))
  562. - return DAG.getNode(RISCVISD::GORC, DL, VT, X,
  563. - DAG.getConstant(RotAmt, DL, VT));
  564. - }
  565. - return SDValue();
  566. - };
  567. -
  568. - // Check for either commutable permutation of (or (GREVI x, shamt), x)
  569. - if (SDValue V = MatchOROfReverse(Op0, Op1))
  570. - return V;
  571. - if (SDValue V = MatchOROfReverse(Op1, Op0))
  572. - return V;
  573. -
  574. - // OR is commutable so canonicalize its OR operand to the left
  575. - if (Op0.getOpcode() != ISD::OR && Op1.getOpcode() == ISD::OR)
  576. - std::swap(Op0, Op1);
  577. - if (Op0.getOpcode() != ISD::OR)
  578. - return SDValue();
  579. - SDValue OrOp0 = Op0.getOperand(0);
  580. - SDValue OrOp1 = Op0.getOperand(1);
  581. - auto LHS = matchGREVIPat(OrOp0);
  582. - // OR is commutable so swap the operands and try again: x might have been
  583. - // on the left
  584. - if (!LHS) {
  585. - std::swap(OrOp0, OrOp1);
  586. - LHS = matchGREVIPat(OrOp0);
  587. - }
  588. - auto RHS = matchGREVIPat(Op1);
  589. - if (LHS && RHS && LHS->formsPairWith(*RHS) && LHS->Op == OrOp1) {
  590. - return DAG.getNode(RISCVISD::GORC, DL, VT, LHS->Op,
  591. - DAG.getConstant(LHS->ShAmt, DL, VT));
  592. - }
  593. - }
  594. - return SDValue();
  595. -}
  596. -
  597. // Matches any of the following bit-manipulation patterns:
  598. // (and (shl x, 1), (0x22222222 << 1))
  599. // (and (srl x, 1), 0x22222222)
  600. @@ -6166,80 +5942,6 @@ static Optional<RISCVBitmanipPat> matchSHFLPat(SDValue Op) {
  601. return matchRISCVBitmanipPat(Op, BitmanipMasks);
  602. }
  603. -// Match (or (or (SHFL_SHL x), (SHFL_SHR x)), (SHFL_AND x)
  604. -static SDValue combineORToSHFL(SDValue Op, SelectionDAG &DAG,
  605. - const RISCVSubtarget &Subtarget) {
  606. - assert(Subtarget.hasStdExtZbp() && "Expected Zbp extenson");
  607. - EVT VT = Op.getValueType();
  608. -
  609. - if (VT != MVT::i32 && VT != Subtarget.getXLenVT())
  610. - return SDValue();
  611. -
  612. - SDValue Op0 = Op.getOperand(0);
  613. - SDValue Op1 = Op.getOperand(1);
  614. -
  615. - // Or is commutable so canonicalize the second OR to the LHS.
  616. - if (Op0.getOpcode() != ISD::OR)
  617. - std::swap(Op0, Op1);
  618. - if (Op0.getOpcode() != ISD::OR)
  619. - return SDValue();
  620. -
  621. - // We found an inner OR, so our operands are the operands of the inner OR
  622. - // and the other operand of the outer OR.
  623. - SDValue A = Op0.getOperand(0);
  624. - SDValue B = Op0.getOperand(1);
  625. - SDValue C = Op1;
  626. -
  627. - auto Match1 = matchSHFLPat(A);
  628. - auto Match2 = matchSHFLPat(B);
  629. -
  630. - // If neither matched, we failed.
  631. - if (!Match1 && !Match2)
  632. - return SDValue();
  633. -
  634. - // We had at least one match. if one failed, try the remaining C operand.
  635. - if (!Match1) {
  636. - std::swap(A, C);
  637. - Match1 = matchSHFLPat(A);
  638. - if (!Match1)
  639. - return SDValue();
  640. - } else if (!Match2) {
  641. - std::swap(B, C);
  642. - Match2 = matchSHFLPat(B);
  643. - if (!Match2)
  644. - return SDValue();
  645. - }
  646. - assert(Match1 && Match2);
  647. -
  648. - // Make sure our matches pair up.
  649. - if (!Match1->formsPairWith(*Match2))
  650. - return SDValue();
  651. -
  652. - // All the remains is to make sure C is an AND with the same input, that masks
  653. - // out the bits that are being shuffled.
  654. - if (C.getOpcode() != ISD::AND || !isa<ConstantSDNode>(C.getOperand(1)) ||
  655. - C.getOperand(0) != Match1->Op)
  656. - return SDValue();
  657. -
  658. - uint64_t Mask = C.getConstantOperandVal(1);
  659. -
  660. - static const uint64_t BitmanipMasks[] = {
  661. - 0x9999999999999999ULL, 0xC3C3C3C3C3C3C3C3ULL, 0xF00FF00FF00FF00FULL,
  662. - 0xFF0000FFFF0000FFULL, 0xFFFF00000000FFFFULL,
  663. - };
  664. -
  665. - unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32;
  666. - unsigned MaskIdx = Log2_32(Match1->ShAmt);
  667. - uint64_t ExpMask = BitmanipMasks[MaskIdx] & maskTrailingOnes<uint64_t>(Width);
  668. -
  669. - if (Mask != ExpMask)
  670. - return SDValue();
  671. -
  672. - SDLoc DL(Op);
  673. - return DAG.getNode(RISCVISD::SHFL, DL, VT, Match1->Op,
  674. - DAG.getConstant(Match1->ShAmt, DL, VT));
  675. -}
  676. -
  677. // Optimize (add (shl x, c0), (shl y, c1)) ->
  678. // (SLLI (SH*ADD x, y), c0), if c1-c0 equals to [1|2|3].
  679. static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
  680. @@ -6465,15 +6167,6 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG) {
  681. static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
  682. const RISCVSubtarget &Subtarget) {
  683. - if (Subtarget.hasStdExtZbp()) {
  684. - if (auto GREV = combineORToGREV(SDValue(N, 0), DAG, Subtarget))
  685. - return GREV;
  686. - if (auto GORC = combineORToGORC(SDValue(N, 0), DAG, Subtarget))
  687. - return GORC;
  688. - if (auto SHFL = combineORToSHFL(SDValue(N, 0), DAG, Subtarget))
  689. - return SHFL;
  690. - }
  691. -
  692. // fold (or (select cond, 0, y), x) ->
  693. // (select cond, x, (or x, y))
  694. return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
  695. @@ -7159,7 +6852,7 @@ bool RISCVTargetLowering::targetShrinkDemandedConstant(
  696. return false;
  697. // Preserve (and X, 0xffff) when zext.h is supported.
  698. - if (Subtarget.hasStdExtZbb() || Subtarget.hasStdExtZbp()) {
  699. + if (Subtarget.hasStdExtZbb()) {
  700. APInt NewMask = APInt(Mask.getBitWidth(), 0xffff);
  701. if (IsLegalMask(NewMask))
  702. return UseMask(NewMask);
  703. diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  704. index a6e2710949b2..d82e414a3f98 100644
  705. --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  706. +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
  707. @@ -322,6 +322,18 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
  708. let Opcode = opcode.Value;
  709. }
  710. +class RVInstCache<bits<12> cache, RISCVOpcode opcode, dag outs, dag ins,
  711. + string opcodestr, string argstr>
  712. + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
  713. + bits<5> rs1;
  714. +
  715. + let Inst{31-20} = cache;
  716. + let Inst{19-15} = rs1;
  717. + let Inst{14-12} = 0;
  718. + let Inst{11-7} = 0;
  719. + let Opcode = opcode.Value;
  720. +}
  721. +
  722. class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
  723. dag outs, dag ins, string opcodestr, string argstr>
  724. : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
  725. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  726. index 575df86d27a8..ea009dc98101 100644
  727. --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  728. +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
  729. @@ -446,6 +446,12 @@ class CSR_ir<bits<3> funct3, string opcodestr>
  730. : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
  731. opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
  732. +let hasNoSchedulingInfo = 1,
  733. + hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  734. +class CSR_cache<bits<12> cache, string opcodestr>
  735. + : RVInstCache<cache, OPC_SYSTEM, (outs), (ins GPR:$rs1),
  736. + opcodestr, "$rs1">, Sched<[WriteCSR, ReadCSR]>;
  737. +
  738. let hasNoSchedulingInfo = 1,
  739. hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
  740. class CSR_ii<bits<3> funct3, string opcodestr>
  741. @@ -588,6 +594,13 @@ def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", "">,
  742. }
  743. } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
  744. +/* Custom instruction and CSRs */
  745. +def CFLUSH_D_L1 : CSR_cache<0b111111000000, "cflush.d.l1">;
  746. +def CDISCARD_D_L1 : CSR_cache<0b111111000010, "cdiscard.d.l1">;
  747. +def CFLUSH_D_L2 : CSR_cache<0b111111000100, "cflush.d.l2">;
  748. +def CDISCARD_D_L2 : CSR_cache<0b111111000110, "cdiscard.d.l2">;
  749. +/* End */
  750. +
  751. def CSRRW : CSR_ir<0b001, "csrrw">;
  752. def CSRRS : CSR_ir<0b010, "csrrs">;
  753. def CSRRC : CSR_ir<0b011, "csrrc">;
  754. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  755. index d2e77ae86a83..7f4985ab4940 100644
  756. --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  757. +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  758. @@ -299,14 +299,14 @@ class RVBTernaryImm5<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
  759. // Instructions
  760. //===----------------------------------------------------------------------===//
  761. -let Predicates = [HasStdExtZbbOrZbp] in {
  762. +let Predicates = [HasStdExtZbb] in {
  763. def ANDN : ALU_rr<0b0100000, 0b111, "andn">,
  764. Sched<[WriteIALU, ReadIALU, ReadIALU]>;
  765. def ORN : ALU_rr<0b0100000, 0b110, "orn">,
  766. Sched<[WriteIALU, ReadIALU, ReadIALU]>;
  767. def XNOR : ALU_rr<0b0100000, 0b100, "xnor">,
  768. Sched<[WriteIALU, ReadIALU, ReadIALU]>;
  769. -} // Predicates = [HasStdExtZbbOrZbp]
  770. +} // Predicates = [HasStdExtZbb]
  771. let Predicates = [HasStdExtZba] in {
  772. def SH1ADD : ALU_rr<0b0010000, 0b010, "sh1add">,
  773. @@ -317,12 +317,12 @@ def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
  774. Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
  775. } // Predicates = [HasStdExtZba]
  776. -let Predicates = [HasStdExtZbbOrZbp] in {
  777. +let Predicates = [HasStdExtZbb] in {
  778. def ROL : ALU_rr<0b0110000, 0b001, "rol">,
  779. Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
  780. def ROR : ALU_rr<0b0110000, 0b101, "ror">,
  781. Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
  782. -} // Predicates = [HasStdExtZbbOrZbp]
  783. +} // Predicates = [HasStdExtZbb]
  784. let Predicates = [HasStdExtZbs] in {
  785. def BCLR : ALU_rr<0b0100100, 0b001, "bclr">, Sched<[]>;
  786. @@ -331,18 +331,7 @@ def BINV : ALU_rr<0b0110100, 0b001, "binv">, Sched<[]>;
  787. def BEXT : ALU_rr<0b0100100, 0b101, "bext">, Sched<[]>;
  788. } // Predicates = [HasStdExtZbs]
  789. -let Predicates = [HasStdExtZbp] in {
  790. -def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
  791. -def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
  792. -} // Predicates = [HasStdExtZbp]
  793. -
  794. -let Predicates = [HasStdExtZbp] in {
  795. -def XPERMN : ALU_rr<0b0010100, 0b010, "xperm.n">, Sched<[]>;
  796. -def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
  797. -def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
  798. -} // Predicates = [HasStdExtZbp]
  799. -
  800. -let Predicates = [HasStdExtZbbOrZbp] in
  801. +let Predicates = [HasStdExtZbb] in
  802. def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
  803. Sched<[WriteRotateImm, ReadRotateImm]>;
  804. @@ -353,24 +342,6 @@ def BINVI : RVBShift_ri<0b01101, 0b001, OPC_OP_IMM, "binvi">, Sched<[]>;
  805. def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">, Sched<[]>;
  806. } // Predicates = [HasStdExtZbs]
  807. -let Predicates = [HasStdExtZbp] in {
  808. -def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>;
  809. -def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>;
  810. -} // Predicates = [HasStdExtZbp]
  811. -
  812. -let Predicates = [HasStdExtZbt] in {
  813. -def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">,
  814. - Sched<[]>;
  815. -def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">,
  816. - Sched<[]>;
  817. -def FSL : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">,
  818. - Sched<[]>;
  819. -def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
  820. - Sched<[]>;
  821. -def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri",
  822. - "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
  823. -} // Predicates = [HasStdExtZbt]
  824. -
  825. let Predicates = [HasStdExtZbb] in {
  826. def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0010011>, "clz">,
  827. Sched<[WriteCLZ, ReadCLZ]>;
  828. @@ -380,10 +351,6 @@ def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0010011>, "cpop">,
  829. Sched<[WriteCPOP, ReadCPOP]>;
  830. } // Predicates = [HasStdExtZbb]
  831. -let Predicates = [HasStdExtZbm, IsRV64] in
  832. -def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, RISCVOpcode<0b0010011>,
  833. - "bmatflip">, Sched<[]>;
  834. -
  835. let Predicates = [HasStdExtZbb] in {
  836. def SEXTB : RVBUnary<0b0110000, 0b00100, 0b001, RISCVOpcode<0b0010011>,
  837. "sext.b">, Sched<[WriteIALU, ReadIALU]>;
  838. @@ -391,32 +358,6 @@ def SEXTH : RVBUnary<0b0110000, 0b00101, 0b001, RISCVOpcode<0b0010011>,
  839. "sext.h">, Sched<[WriteIALU, ReadIALU]>;
  840. } // Predicates = [HasStdExtZbb]
  841. -let Predicates = [HasStdExtZbr] in {
  842. -def CRC32B : RVBUnary<0b0110000, 0b10000, 0b001, RISCVOpcode<0b0010011>,
  843. - "crc32.b">, Sched<[]>;
  844. -def CRC32H : RVBUnary<0b0110000, 0b10001, 0b001, RISCVOpcode<0b0010011>,
  845. - "crc32.h">, Sched<[]>;
  846. -def CRC32W : RVBUnary<0b0110000, 0b10010, 0b001, RISCVOpcode<0b0010011>,
  847. - "crc32.w">, Sched<[]>;
  848. -} // Predicates = [HasStdExtZbr]
  849. -
  850. -let Predicates = [HasStdExtZbr, IsRV64] in
  851. -def CRC32D : RVBUnary<0b0110000, 0b10011, 0b001, RISCVOpcode<0b0010011>,
  852. - "crc32.d">, Sched<[]>;
  853. -
  854. -let Predicates = [HasStdExtZbr] in {
  855. -def CRC32CB : RVBUnary<0b0110000, 0b11000, 0b001, RISCVOpcode<0b0010011>,
  856. - "crc32c.b">, Sched<[]>;
  857. -def CRC32CH : RVBUnary<0b0110000, 0b11001, 0b001, RISCVOpcode<0b0010011>,
  858. - "crc32c.h">, Sched<[]>;
  859. -def CRC32CW : RVBUnary<0b0110000, 0b11010, 0b001, RISCVOpcode<0b0010011>,
  860. - "crc32c.w">, Sched<[]>;
  861. -} // Predicates = [HasStdExtZbr]
  862. -
  863. -let Predicates = [HasStdExtZbr, IsRV64] in
  864. -def CRC32CD : RVBUnary<0b0110000, 0b11011, 0b001, RISCVOpcode<0b0010011>,
  865. - "crc32c.d">, Sched<[]>;
  866. -
  867. let Predicates = [HasStdExtZbc] in {
  868. def CLMUL : ALU_rr<0b0000101, 0b001, "clmul">, Sched<[]>;
  869. def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">, Sched<[]>;
  870. @@ -434,37 +375,6 @@ def MAXU : ALU_rr<0b0000101, 0b111, "maxu">,
  871. Sched<[WriteIALU, ReadIALU, ReadIALU]>;
  872. } // Predicates = [HasStdExtZbb]
  873. -let Predicates = [HasStdExtZbp] in {
  874. -def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
  875. -def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
  876. -} // Predicates = [HasStdExtZbp]
  877. -
  878. -let Predicates = [HasStdExtZbe] in {
  879. -// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
  880. -// bext in the 0.93 spec.
  881. -def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
  882. -def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
  883. -} // Predicates = [HasStdExtZbe]
  884. -
  885. -let Predicates = [HasStdExtZbp] in {
  886. -def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
  887. -def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
  888. -def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
  889. -} // Predicates = [HasStdExtZbp]
  890. -
  891. -let Predicates = [HasStdExtZbm, IsRV64] in {
  892. -def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
  893. -def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
  894. -} // Predicates = [HasStdExtZbm, IsRV64]
  895. -
  896. -let Predicates = [HasStdExtZbf] in
  897. -def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
  898. -
  899. -let Predicates = [HasStdExtZbp] in {
  900. -def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
  901. -def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
  902. -} // Predicates = [HasStdExtZbp]
  903. -
  904. let Predicates = [HasStdExtZba, IsRV64] in {
  905. def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">,
  906. Sched<[WriteShiftImm32, ReadShiftImm32]>;
  907. @@ -476,14 +386,14 @@ def SH2ADDUW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">,
  908. Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
  909. def SH3ADDUW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
  910. Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
  911. -} // Predicates = [HasStdExtZbb, IsRV64]
  912. +} // Predicates = [HasStdExtZba, IsRV64]
  913. -let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
  914. +let Predicates = [HasStdExtZbb, IsRV64] in {
  915. def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
  916. Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
  917. def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
  918. Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
  919. -} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
  920. +} // Predicates = [HasStdExtZbb, IsRV64]
  921. let Predicates = [HasStdExtZbs, IsRV64] in {
  922. // NOTE: These instructions have been removed from the 0.94 spec. As a result
  923. @@ -494,16 +404,7 @@ def BINVW : ALUW_rr<0b0110100, 0b001, "binvw">, Sched<[]>;
  924. def BEXTW : ALUW_rr<0b0100100, 0b101, "bextw">, Sched<[]>;
  925. } // Predicates = [HasStdExtZbs, IsRV64]
  926. -let Predicates = [HasStdExtZbp, IsRV64] in {
  927. -def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
  928. -def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
  929. -} // Predicates = [HasStdExtZbp, IsRV64]
  930. -
  931. -let Predicates = [HasStdExtZbp, IsRV64] in {
  932. -def XPERMW : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
  933. -} // Predicates = [HasStdExtZbp, IsRV64]
  934. -
  935. -let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
  936. +let Predicates = [HasStdExtZbb, IsRV64] in
  937. def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
  938. Sched<[WriteRotateImm32, ReadRotateImm32]>;
  939. @@ -518,20 +419,6 @@ def BINVIW : RVBShiftW_ri<0b0110100, 0b001, OPC_OP_IMM_32, "binviw">,
  940. Sched<[]>;
  941. } // Predicates = [HasStdExtZbs, IsRV64]
  942. -let Predicates = [HasStdExtZbp, IsRV64] in {
  943. -def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
  944. -def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
  945. -} // Predicates = [HasStdExtZbp, IsRV64]
  946. -
  947. -let Predicates = [HasStdExtZbt, IsRV64] in {
  948. -def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32,
  949. - "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
  950. -def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
  951. - "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
  952. -def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
  953. - "fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
  954. -} // Predicates = [HasStdExtZbt, IsRV64]
  955. -
  956. let Predicates = [HasStdExtZbb, IsRV64] in {
  957. def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>,
  958. "clzw">, Sched<[WriteCLZ32, ReadCLZ32]>;
  959. @@ -541,43 +428,23 @@ def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
  960. "cpopw">, Sched<[WriteCPOP32, ReadCPOP32]>;
  961. } // Predicates = [HasStdExtZbb, IsRV64]
  962. -let Predicates = [HasStdExtZbp, IsRV64] in {
  963. -def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
  964. -def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
  965. -} // Predicates = [HasStdExtZbp, IsRV64]
  966. -
  967. -let Predicates = [HasStdExtZbe, IsRV64] in {
  968. -// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
  969. -// bextw in the 0.93 spec.
  970. -def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
  971. -def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
  972. -} // Predicates = [HasStdExtZbe, IsRV64]
  973. -
  974. -let Predicates = [HasStdExtZbp, IsRV64] in {
  975. -def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
  976. -def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
  977. -} // Predicates = [HasStdExtZbp, IsRV64]
  978. -
  979. -let Predicates = [HasStdExtZbf, IsRV64] in
  980. -def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">, Sched<[]>;
  981. -
  982. -let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
  983. +let Predicates = [HasStdExtZbb, IsRV32] in {
  984. let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  985. def ZEXTH_RV32 : RVInstR<0b0000100, 0b100, OPC_OP, (outs GPR:$rd),
  986. (ins GPR:$rs1), "zext.h", "$rd, $rs1">,
  987. Sched<[WriteIALU, ReadIALU]> {
  988. let rs2 = 0b00000;
  989. }
  990. -} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
  991. +} // Predicates = [HasStdExtZbb, IsRV32]
  992. -let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
  993. +let Predicates = [HasStdExtZbb, IsRV64] in {
  994. let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  995. def ZEXTH_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
  996. (ins GPR:$rs1), "zext.h", "$rd, $rs1">,
  997. Sched<[WriteIALU, ReadIALU]> {
  998. let rs2 = 0b00000;
  999. }
  1000. -} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
  1001. +} // Predicates = [HasStdExtZbb, IsRV64]
  1002. // We treat rev8 and orc.b as standalone instructions even though they use a
  1003. // portion of the encodings for grevi and gorci. This allows us to support only
  1004. @@ -586,29 +453,29 @@ def ZEXTH_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
  1005. // causes diagnostics to suggest that Zbp rather than Zbb is required for rev8
  1006. // or gorci. Since Zbb is closer to being finalized than Zbp this will be
  1007. // misleading to users.
  1008. -let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
  1009. +let Predicates = [HasStdExtZbb, IsRV32] in {
  1010. let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  1011. def REV8_RV32 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
  1012. "rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
  1013. let imm12 = { 0b01101, 0b0011000 };
  1014. }
  1015. -} // Predicates = [HasStdExtZbbOrZbp, IsRV32]
  1016. +} // Predicates = [HasStdExtZbb, IsRV32]
  1017. -let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
  1018. +let Predicates = [HasStdExtZbb, IsRV64] in {
  1019. let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  1020. def REV8_RV64 : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
  1021. "rev8", "$rd, $rs1">, Sched<[WriteREV8, ReadREV8]> {
  1022. let imm12 = { 0b01101, 0b0111000 };
  1023. }
  1024. -} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
  1025. +} // Predicates = [HasStdExtZbb, IsRV64]
  1026. -let Predicates = [HasStdExtZbbOrZbp] in {
  1027. +let Predicates = [HasStdExtZbb] in {
  1028. let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
  1029. def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
  1030. "orc.b", "$rd, $rs1">, Sched<[WriteORCB, ReadORCB]> {
  1031. let imm12 = { 0b00101, 0b0000111 };
  1032. }
  1033. -} // Predicates = [HasStdExtZbbOrZbp]
  1034. +} // Predicates = [HasStdExtZbb]
  1035. //===----------------------------------------------------------------------===//
  1036. // Future compressed instructions
  1037. @@ -651,138 +518,15 @@ let Predicates = [HasStdExtZba, IsRV64] in {
  1038. def : InstAlias<"zext.w $rd, $rs", (ADDUW GPR:$rd, GPR:$rs, X0)>;
  1039. }
  1040. -let Predicates = [HasStdExtZbp] in {
  1041. -def : InstAlias<"rev.p $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00001)>;
  1042. -def : InstAlias<"rev2.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00010)>;
  1043. -def : InstAlias<"rev.n $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00011)>;
  1044. -def : InstAlias<"rev4.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00100)>;
  1045. -def : InstAlias<"rev2.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00110)>;
  1046. -def : InstAlias<"rev.b $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b00111)>;
  1047. -def : InstAlias<"rev8.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01000)>;
  1048. -def : InstAlias<"rev4.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01100)>;
  1049. -def : InstAlias<"rev2.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01110)>;
  1050. -def : InstAlias<"rev.h $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b01111)>;
  1051. -
  1052. -def : InstAlias<"zip.n $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0001)>;
  1053. -def : InstAlias<"unzip.n $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0001)>;
  1054. -def : InstAlias<"zip2.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0010)>;
  1055. -def : InstAlias<"unzip2.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0010)>;
  1056. -def : InstAlias<"zip.b $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0011)>;
  1057. -def : InstAlias<"unzip.b $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0011)>;
  1058. -def : InstAlias<"zip4.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0100)>;
  1059. -def : InstAlias<"unzip4.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0100)>;
  1060. -def : InstAlias<"zip2.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0110)>;
  1061. -def : InstAlias<"unzip2.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0110)>;
  1062. -def : InstAlias<"zip.h $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b0111)>;
  1063. -def : InstAlias<"unzip.h $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b0111)>;
  1064. -
  1065. -def : InstAlias<"orc.p $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00001)>;
  1066. -def : InstAlias<"orc2.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00010)>;
  1067. -def : InstAlias<"orc.n $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00011)>;
  1068. -def : InstAlias<"orc4.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00100)>;
  1069. -def : InstAlias<"orc2.b $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b00110)>;
  1070. -// orc.b is considered an instruction rather than an alias.
  1071. -def : InstAlias<"orc8.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01000)>;
  1072. -def : InstAlias<"orc4.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01100)>;
  1073. -def : InstAlias<"orc2.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01110)>;
  1074. -def : InstAlias<"orc.h $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b01111)>;
  1075. -} // Predicates = [HasStdExtZbp]
  1076. -
  1077. -let Predicates = [HasStdExtZbp, IsRV32] in {
  1078. -def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>;
  1079. -// rev8 is considered an instruction rather than an alias.
  1080. -def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>;
  1081. -def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>;
  1082. -def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>;
  1083. -
  1084. -def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1000)>;
  1085. -def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1000)>;
  1086. -def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1100)>;
  1087. -def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1100)>;
  1088. -def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1110)>;
  1089. -def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1110)>;
  1090. -def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b1111)>;
  1091. -def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b1111)>;
  1092. -
  1093. -def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
  1094. -def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;
  1095. -def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11100)>;
  1096. -def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11110)>;
  1097. -def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11111)>;
  1098. -} // Predicates = [HasStdExtZbp, IsRV32]
  1099. -
  1100. -let Predicates = [HasStdExtZbp, IsRV64] in {
  1101. -def : InstAlias<"rev16.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b010000)>;
  1102. -def : InstAlias<"rev8.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011000)>;
  1103. -def : InstAlias<"rev4.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011100)>;
  1104. -def : InstAlias<"rev2.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011110)>;
  1105. -def : InstAlias<"rev.w $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b011111)>;
  1106. -def : InstAlias<"rev32 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b100000)>;
  1107. -def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b110000)>;
  1108. -// rev8 is considered an instruction rather than an alias.
  1109. -def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111100)>;
  1110. -def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111110)>;
  1111. -def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b111111)>;
  1112. -
  1113. -def : InstAlias<"zip8.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01000)>;
  1114. -def : InstAlias<"unzip8.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01000)>;
  1115. -def : InstAlias<"zip4.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01100)>;
  1116. -def : InstAlias<"unzip4.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01100)>;
  1117. -def : InstAlias<"zip2.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01110)>;
  1118. -def : InstAlias<"unzip2.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01110)>;
  1119. -def : InstAlias<"zip.w $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b01111)>;
  1120. -def : InstAlias<"unzip.w $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b01111)>;
  1121. -def : InstAlias<"zip16 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b10000)>;
  1122. -def : InstAlias<"unzip16 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b10000)>;
  1123. -def : InstAlias<"zip8 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11000)>;
  1124. -def : InstAlias<"unzip8 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11000)>;
  1125. -def : InstAlias<"zip4 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11100)>;
  1126. -def : InstAlias<"unzip4 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11100)>;
  1127. -def : InstAlias<"zip2 $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11110)>;
  1128. -def : InstAlias<"unzip2 $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11110)>;
  1129. -def : InstAlias<"zip $rd, $rs", (SHFLI GPR:$rd, GPR:$rs, 0b11111)>;
  1130. -def : InstAlias<"unzip $rd, $rs", (UNSHFLI GPR:$rd, GPR:$rs, 0b11111)>;
  1131. -
  1132. -def : InstAlias<"orc16.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b010000)>;
  1133. -def : InstAlias<"orc8.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011000)>;
  1134. -def : InstAlias<"orc4.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011100)>;
  1135. -def : InstAlias<"orc2.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011110)>;
  1136. -def : InstAlias<"orc.w $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b011111)>;
  1137. -def : InstAlias<"orc32 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b100000)>;
  1138. -def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b110000)>;
  1139. -def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111000)>;
  1140. -def : InstAlias<"orc4 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111100)>;
  1141. -def : InstAlias<"orc2 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111110)>;
  1142. -def : InstAlias<"orc $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b111111)>;
  1143. -} // Predicates = [HasStdExtZbp, IsRV64]
  1144. -
  1145. -let Predicates = [HasStdExtZbbOrZbp] in {
  1146. +let Predicates = [HasStdExtZbb] in {
  1147. def : InstAlias<"ror $rd, $rs1, $shamt",
  1148. (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
  1149. -} // Predicates = [HasStdExtZbbOrZbp]
  1150. +} // Predicates = [HasStdExtZbb]
  1151. -let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
  1152. +let Predicates = [HasStdExtZbb, IsRV64] in {
  1153. def : InstAlias<"rorw $rd, $rs1, $shamt",
  1154. (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
  1155. -} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
  1156. -
  1157. -let Predicates = [HasStdExtZbp] in {
  1158. -def : InstAlias<"grev $rd, $rs1, $shamt",
  1159. - (GREVI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
  1160. -def : InstAlias<"gorc $rd, $rs1, $shamt",
  1161. - (GORCI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
  1162. -def : InstAlias<"shfl $rd, $rs1, $shamt",
  1163. - (SHFLI GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
  1164. -def : InstAlias<"unshfl $rd, $rs1, $shamt",
  1165. - (UNSHFLI GPR:$rd, GPR:$rs1, shfl_uimm:$shamt), 0>;
  1166. -} // Predicates = [HasStdExtZbp]
  1167. -
  1168. -let Predicates = [HasStdExtZbp, IsRV64] in {
  1169. -def : InstAlias<"grevw $rd, $rs1, $shamt",
  1170. - (GREVIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
  1171. -def : InstAlias<"gorcw $rd, $rs1, $shamt",
  1172. - (GORCIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
  1173. -} // Predicates = [HasStdExtZbp, IsRV64]
  1174. +} // Predicates = [HasStdExtZbb, IsRV64]
  1175. let Predicates = [HasStdExtZbs] in {
  1176. def : InstAlias<"bset $rd, $rs1, $shamt",
  1177. @@ -814,16 +558,16 @@ def : CompressPat<(ADDUW GPRC:$rs1, GPRC:$rs1, X0),
  1178. // Codegen patterns
  1179. //===----------------------------------------------------------------------===//
  1180. -let Predicates = [HasStdExtZbbOrZbp] in {
  1181. +let Predicates = [HasStdExtZbb] in {
  1182. def : Pat<(and GPR:$rs1, (not GPR:$rs2)), (ANDN GPR:$rs1, GPR:$rs2)>;
  1183. def : Pat<(or GPR:$rs1, (not GPR:$rs2)), (ORN GPR:$rs1, GPR:$rs2)>;
  1184. def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
  1185. -} // Predicates = [HasStdExtZbbOrZbp]
  1186. +} // Predicates = [HasStdExtZbb]
  1187. -let Predicates = [HasStdExtZbbOrZbp] in {
  1188. +let Predicates = [HasStdExtZbb] in {
  1189. def : PatGprGpr<rotl, ROL>;
  1190. def : PatGprGpr<rotr, ROR>;
  1191. -} // Predicates = [HasStdExtZbbOrZbp]
  1192. +} // Predicates = [HasStdExtZbb]
  1193. let Predicates = [HasStdExtZbs] in {
  1194. def : Pat<(and (not (shiftop<shl> 1, GPR:$rs2)), GPR:$rs1),
  1195. @@ -871,7 +615,7 @@ def : Pat<(and GPR:$r, BCLRIANDIMask:$i),
  1196. // There's no encoding for roli in the the 'B' extension as it can be
  1197. // implemented with rori by negating the immediate.
  1198. -let Predicates = [HasStdExtZbbOrZbp] in {
  1199. +let Predicates = [HasStdExtZbb] in {
  1200. def : PatGprImm<rotr, RORI, uimmlog2xlen>;
  1201. def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
  1202. (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
  1203. @@ -881,80 +625,6 @@ def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
  1204. def : Pat<(riscv_gorc GPR:$rs1, 7), (ORCB GPR:$rs1)>;
  1205. }
  1206. -let Predicates = [HasStdExtZbp] in {
  1207. -def : PatGprGpr<riscv_grev, GREV>;
  1208. -def : PatGprGpr<riscv_gorc, GORC>;
  1209. -def : PatGprGpr<riscv_shfl, SHFL>;
  1210. -def : PatGprGpr<riscv_unshfl, UNSHFL>;
  1211. -def : PatGprGpr<int_riscv_xperm_n, XPERMN>;
  1212. -def : PatGprGpr<int_riscv_xperm_b, XPERMB>;
  1213. -def : PatGprGpr<int_riscv_xperm_h, XPERMH>;
  1214. -def : PatGprGpr<int_riscv_xperm_w, XPERMW>;
  1215. -def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>;
  1216. -def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
  1217. -def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>;
  1218. -def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>;
  1219. -} // Predicates = [HasStdExtZbp]
  1220. -
  1221. -let Predicates = [HasStdExtZbp, IsRV32] in {
  1222. -def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
  1223. -def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
  1224. -
  1225. -// We treat rev8 as a separate instruction, so match it directly.
  1226. -def : Pat<(i32 (riscv_grev GPR:$rs1, 24)), (REV8_RV32 GPR:$rs1)>;
  1227. -} // Predicates = [HasStdExtZbp, IsRV32]
  1228. -
  1229. -let Predicates = [HasStdExtZbp, IsRV64] in {
  1230. -// We treat rev8 as a separate instruction, so match it directly.
  1231. -def : Pat<(i64 (riscv_grev GPR:$rs1, 56)), (REV8_RV64 GPR:$rs1)>;
  1232. -} // Predicates = [HasStdExtZbp, IsRV64]
  1233. -
  1234. -let Predicates = [HasStdExtZbt] in {
  1235. -def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)),
  1236. - (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
  1237. -
  1238. -def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3),
  1239. - (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
  1240. -def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1),
  1241. - (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
  1242. -def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3),
  1243. - (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
  1244. -def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1),
  1245. - (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
  1246. -def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
  1247. - (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
  1248. -def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
  1249. - (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
  1250. -def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
  1251. - (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
  1252. -def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
  1253. - (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
  1254. -def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
  1255. - (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
  1256. -def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
  1257. - (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
  1258. -def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
  1259. - (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
  1260. -} // Predicates = [HasStdExtZbt]
  1261. -
  1262. -// fshl and fshr concatenate their operands in the same order. fsr and fsl
  1263. -// instruction use different orders. fshl will return its first operand for
  1264. -// shift of zero, fshr will return its second operand. fsl and fsr both return
  1265. -// $rs1 so the patterns need to have different operand orders.
  1266. -let Predicates = [HasStdExtZbt] in {
  1267. -def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2),
  1268. - (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
  1269. -def : Pat<(riscv_fsr GPR:$rs3, GPR:$rs1, GPR:$rs2),
  1270. - (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
  1271. -
  1272. -def : Pat<(fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
  1273. - (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>;
  1274. -// We can use FSRI for fshl by immediate if we subtract the immediate from
  1275. -// XLen and swap the operands.
  1276. -def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
  1277. - (FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
  1278. -} // Predicates = [HasStdExtZbt]
  1279. -
  1280. let Predicates = [HasStdExtZbb] in {
  1281. def : PatGpr<ctlz, CLZ>;
  1282. def : PatGpr<cttz, CTZ>;
  1283. @@ -981,27 +651,9 @@ let Predicates = [HasStdExtZbb, IsRV64] in {
  1284. def : Pat<(i64 (bswap GPR:$rs1)), (REV8_RV64 GPR:$rs1)>;
  1285. } // Predicates = [HasStdExtZbb, IsRV64]
  1286. -let Predicates = [HasStdExtZbp, IsRV32] in {
  1287. -def : Pat<(i32 (or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16)))),
  1288. - (PACK GPR:$rs1, GPR:$rs2)>;
  1289. -def : Pat<(i32 (or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16)))),
  1290. - (PACKU GPR:$rs1, GPR:$rs2)>;
  1291. -
  1292. -}
  1293. -let Predicates = [HasStdExtZbp, IsRV64] in {
  1294. -def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))),
  1295. - (PACK GPR:$rs1, GPR:$rs2)>;
  1296. -def : Pat<(i64 (or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32)))),
  1297. - (PACKU GPR:$rs1, GPR:$rs2)>;
  1298. -}
  1299. -let Predicates = [HasStdExtZbp] in
  1300. -def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
  1301. - (and GPR:$rs1, 0x00FF)),
  1302. - (PACKH GPR:$rs1, GPR:$rs2)>;
  1303. -
  1304. -let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
  1305. +let Predicates = [HasStdExtZbb, IsRV32] in
  1306. def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV32 GPR:$rs)>;
  1307. -let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
  1308. +let Predicates = [HasStdExtZbb, IsRV64] in
  1309. def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXTH_RV64 GPR:$rs)>;
  1310. // Pattern to exclude simm12 immediates from matching.
  1311. @@ -1100,35 +752,13 @@ def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF), non_imm12:$rs2))
  1312. (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
  1313. } // Predicates = [HasStdExtZba, IsRV64]
  1314. -let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
  1315. +let Predicates = [HasStdExtZbb, IsRV64] in {
  1316. def : PatGprGpr<riscv_rolw, ROLW>;
  1317. def : PatGprGpr<riscv_rorw, RORW>;
  1318. def : PatGprImm<riscv_rorw, RORIW, uimm5>;
  1319. def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
  1320. (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
  1321. -} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
  1322. -
  1323. -let Predicates = [HasStdExtZbp, IsRV64] in {
  1324. -def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
  1325. -def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
  1326. -def : PatGprGpr<riscv_grevw, GREVW>;
  1327. -def : PatGprGpr<riscv_gorcw, GORCW>;
  1328. -def : PatGprGpr<riscv_shflw, SHFLW>;
  1329. -def : PatGprGpr<riscv_unshflw, UNSHFLW>;
  1330. -def : PatGprImm<riscv_grevw, GREVIW, uimm5>;
  1331. -def : PatGprImm<riscv_gorcw, GORCIW, uimm5>;
  1332. -} // Predicates = [HasStdExtZbp, IsRV64]
  1333. -
  1334. -let Predicates = [HasStdExtZbt, IsRV64] in {
  1335. -def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
  1336. - (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
  1337. -def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2),
  1338. - (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
  1339. -def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
  1340. - (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>;
  1341. -def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
  1342. - (FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>;
  1343. -} // Predicates = [HasStdExtZbt, IsRV64]
  1344. +} // Predicates = [HasStdExtZbb, IsRV64]
  1345. let Predicates = [HasStdExtZbb, IsRV64] in {
  1346. def : PatGpr<riscv_clzw, CLZW>;
  1347. @@ -1136,45 +766,8 @@ def : PatGpr<riscv_ctzw, CTZW>;
  1348. def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;
  1349. } // Predicates = [HasStdExtZbb, IsRV64]
  1350. -let Predicates = [HasStdExtZbp, IsRV64] in {
  1351. -def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
  1352. - (and GPR:$rs1, 0x000000000000FFFF)),
  1353. - i32)),
  1354. - (PACKW GPR:$rs1, GPR:$rs2)>;
  1355. -def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
  1356. - (and GPR:$rs1, 0x000000000000FFFF))),
  1357. - (PACKW GPR:$rs1, GPR:$rs2)>;
  1358. -def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
  1359. - (srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
  1360. - (PACKUW GPR:$rs1, GPR:$rs2)>;
  1361. -} // Predicates = [HasStdExtZbp, IsRV64]
  1362. -
  1363. let Predicates = [HasStdExtZbc] in {
  1364. def : PatGprGpr<int_riscv_clmul, CLMUL>;
  1365. def : PatGprGpr<int_riscv_clmulh, CLMULH>;
  1366. def : PatGprGpr<int_riscv_clmulr, CLMULR>;
  1367. -} // Predicates = [HasStdExtZbc]
  1368. -
  1369. -let Predicates = [HasStdExtZbe] in {
  1370. -def : PatGprGpr<riscv_bcompress, BCOMPRESS>;
  1371. -def : PatGprGpr<riscv_bdecompress, BDECOMPRESS>;
  1372. -} // Predicates = [HasStdExtZbe]
  1373. -
  1374. -let Predicates = [HasStdExtZbe, IsRV64] in {
  1375. -def : PatGprGpr<riscv_bcompressw, BCOMPRESSW>;
  1376. -def : PatGprGpr<riscv_bdecompressw, BDECOMPRESSW>;
  1377. -} // Predicates = [HasStdExtZbe, IsRV64]
  1378. -
  1379. -let Predicates = [HasStdExtZbr] in {
  1380. -def : PatGpr<int_riscv_crc32_b, CRC32B>;
  1381. -def : PatGpr<int_riscv_crc32_h, CRC32H>;
  1382. -def : PatGpr<int_riscv_crc32_w, CRC32W>;
  1383. -def : PatGpr<int_riscv_crc32c_b, CRC32CB>;
  1384. -def : PatGpr<int_riscv_crc32c_h, CRC32CH>;
  1385. -def : PatGpr<int_riscv_crc32c_w, CRC32CW>;
  1386. -} // Predicates = [HasStdExtZbr]
  1387. -
  1388. -let Predicates = [HasStdExtZbr, IsRV64] in {
  1389. -def : PatGpr<int_riscv_crc32_d, CRC32D>;
  1390. -def : PatGpr<int_riscv_crc32c_d, CRC32CD>;
  1391. -} // Predicates = [HasStdExtZbr, IsRV64]
  1392. +} // Predicates = [HasStdExtZbc]
  1393. \ No newline at end of file
  1394. --
  1395. 2.33.1