0001-Merge-B-instruction-from-0p94-to-1.0.patch 9.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207
  1. From fb2eb2b94ec405ee159ef7615d3745aa6178bff6 Mon Sep 17 00:00:00 2001
  2. From: "yilun.xie" <yilun.xie@starfivetech.com>
  3. Date: Mon, 25 Oct 2021 17:04:21 +0800
  4. Subject: [PATCH 1/3] Merge B instruction from 0p94 to 1.0
  5. ---
  6. .arcconfig | 0
  7. .arclint | 0
  8. .clang-format | 0
  9. .clang-tidy | 0
  10. .git-blame-ignore-revs | 0
  11. .github/lockdown.yml | 0
  12. .github/workflows/README.md | 0
  13. .gitignore | 0
  14. clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 14 ++++-------
  15. .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 24 +++++++++----------
  16. .../MCTargetDesc/RISCVTargetStreamer.cpp | 24 +++++++++----------
  17. llvm/lib/Target/RISCV/RISCV.td | 8 +------
  18. 12 files changed, 30 insertions(+), 40 deletions(-)
  19. mode change 100644 => 100755 .arcconfig
  20. mode change 100644 => 100755 .arclint
  21. mode change 100644 => 100755 .clang-format
  22. mode change 100644 => 100755 .clang-tidy
  23. mode change 100644 => 100755 .git-blame-ignore-revs
  24. mode change 100644 => 100755 .github/lockdown.yml
  25. mode change 100644 => 100755 .github/workflows/README.md
  26. mode change 100644 => 100755 .gitignore
  27. diff --git a/.arcconfig b/.arcconfig
  28. old mode 100644
  29. new mode 100755
  30. diff --git a/.arclint b/.arclint
  31. old mode 100644
  32. new mode 100755
  33. diff --git a/.clang-format b/.clang-format
  34. old mode 100644
  35. new mode 100755
  36. diff --git a/.clang-tidy b/.clang-tidy
  37. old mode 100644
  38. new mode 100755
  39. diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs
  40. old mode 100644
  41. new mode 100755
  42. diff --git a/.github/lockdown.yml b/.github/lockdown.yml
  43. old mode 100644
  44. new mode 100755
  45. diff --git a/.github/workflows/README.md b/.github/workflows/README.md
  46. old mode 100644
  47. new mode 100755
  48. diff --git a/.gitignore b/.gitignore
  49. old mode 100644
  50. new mode 100755
  51. diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  52. index ade93d6881a7..f54ac5b166d4 100644
  53. --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  54. +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  55. @@ -59,9 +59,11 @@ static StringRef getExtensionType(StringRef Ext) {
  56. static Optional<RISCVExtensionVersion>
  57. isExperimentalExtension(StringRef Ext) {
  58. if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
  59. - Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
  60. - Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
  61. - return RISCVExtensionVersion{"0", "93"};
  62. + Ext == "zbs")
  63. + return RISCVExtensionVersion{"1", "0"};
  64. + if (Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
  65. + Ext == "zbr" || Ext == "zbt" || Ext == "zbproposedc")
  66. + return RISCVExtensionVersion{"0", "94"};
  67. if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
  68. return RISCVExtensionVersion{"0", "10"};
  69. if (Ext == "zfh")
  70. @@ -422,13 +424,7 @@ static bool getArchFeatures(const Driver &D, StringRef MArch,
  71. Features.push_back("+experimental-zba");
  72. Features.push_back("+experimental-zbb");
  73. Features.push_back("+experimental-zbc");
  74. - Features.push_back("+experimental-zbe");
  75. - Features.push_back("+experimental-zbf");
  76. - Features.push_back("+experimental-zbm");
  77. - Features.push_back("+experimental-zbp");
  78. - Features.push_back("+experimental-zbr");
  79. Features.push_back("+experimental-zbs");
  80. - Features.push_back("+experimental-zbt");
  81. break;
  82. case 'v':
  83. Features.push_back("+experimental-v");
  84. diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  85. index ddf07b808d03..17548b7141a3 100644
  86. --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  87. +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  88. @@ -2192,33 +2192,33 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
  89. if (getFeatureBits(RISCV::FeatureStdExtC))
  90. formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
  91. if (getFeatureBits(RISCV::FeatureStdExtB))
  92. - formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
  93. + formalArchStr = (Twine(formalArchStr) + "_b1p0").str();
  94. if (getFeatureBits(RISCV::FeatureStdExtV))
  95. formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
  96. if (getFeatureBits(RISCV::FeatureStdExtZfh))
  97. formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
  98. if (getFeatureBits(RISCV::FeatureStdExtZba))
  99. - formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
  100. + formalArchStr = (Twine(formalArchStr) + "_zba1p0").str();
  101. if (getFeatureBits(RISCV::FeatureStdExtZbb))
  102. - formalArchStr = (Twine(formalArchStr) + "_zbb0p93").str();
  103. + formalArchStr = (Twine(formalArchStr) + "_zbb1p0").str();
  104. if (getFeatureBits(RISCV::FeatureStdExtZbc))
  105. - formalArchStr = (Twine(formalArchStr) + "_zbc0p93").str();
  106. + formalArchStr = (Twine(formalArchStr) + "_zbc1p0").str();
  107. if (getFeatureBits(RISCV::FeatureStdExtZbe))
  108. - formalArchStr = (Twine(formalArchStr) + "_zbe0p93").str();
  109. + formalArchStr = (Twine(formalArchStr) + "_zbe0p94").str();
  110. if (getFeatureBits(RISCV::FeatureStdExtZbf))
  111. - formalArchStr = (Twine(formalArchStr) + "_zbf0p93").str();
  112. + formalArchStr = (Twine(formalArchStr) + "_zbf0p94").str();
  113. if (getFeatureBits(RISCV::FeatureStdExtZbm))
  114. - formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str();
  115. + formalArchStr = (Twine(formalArchStr) + "_zbm0p94").str();
  116. if (getFeatureBits(RISCV::FeatureStdExtZbp))
  117. - formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str();
  118. + formalArchStr = (Twine(formalArchStr) + "_zbp0p94").str();
  119. if (getFeatureBits(RISCV::FeatureStdExtZbproposedc))
  120. - formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
  121. + formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p94").str();
  122. if (getFeatureBits(RISCV::FeatureStdExtZbr))
  123. - formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
  124. + formalArchStr = (Twine(formalArchStr) + "_zbr0p94").str();
  125. if (getFeatureBits(RISCV::FeatureStdExtZbs))
  126. - formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
  127. + formalArchStr = (Twine(formalArchStr) + "_zbs1p0").str();
  128. if (getFeatureBits(RISCV::FeatureStdExtZbt))
  129. - formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
  130. + formalArchStr = (Twine(formalArchStr) + "_zbt0p94").str();
  131. if (getFeatureBits(RISCV::FeatureStdExtZvamo))
  132. formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();
  133. if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
  134. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  135. index fd6e49d02c22..14b54fb83097 100644
  136. --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  137. +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
  138. @@ -61,33 +61,33 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
  139. if (STI.hasFeature(RISCV::FeatureStdExtC))
  140. Arch += "_c2p0";
  141. if (STI.hasFeature(RISCV::FeatureStdExtB))
  142. - Arch += "_b0p93";
  143. + Arch += "_b1p0";
  144. if (STI.hasFeature(RISCV::FeatureStdExtV))
  145. Arch += "_v0p10";
  146. if (STI.hasFeature(RISCV::FeatureStdExtZfh))
  147. Arch += "_zfh0p1";
  148. if (STI.hasFeature(RISCV::FeatureStdExtZba))
  149. - Arch += "_zba0p93";
  150. + Arch += "_zba1p0";
  151. if (STI.hasFeature(RISCV::FeatureStdExtZbb))
  152. - Arch += "_zbb0p93";
  153. + Arch += "_zbb1p0";
  154. if (STI.hasFeature(RISCV::FeatureStdExtZbc))
  155. - Arch += "_zbc0p93";
  156. + Arch += "_zbc1p0";
  157. if (STI.hasFeature(RISCV::FeatureStdExtZbe))
  158. - Arch += "_zbe0p93";
  159. + Arch += "_zbe0p94";
  160. if (STI.hasFeature(RISCV::FeatureStdExtZbf))
  161. - Arch += "_zbf0p93";
  162. + Arch += "_zbf0p94";
  163. if (STI.hasFeature(RISCV::FeatureStdExtZbm))
  164. - Arch += "_zbm0p93";
  165. + Arch += "_zbm0p94";
  166. if (STI.hasFeature(RISCV::FeatureStdExtZbp))
  167. - Arch += "_zbp0p93";
  168. + Arch += "_zbp0p94";
  169. if (STI.hasFeature(RISCV::FeatureStdExtZbproposedc))
  170. - Arch += "_zbproposedc0p93";
  171. + Arch += "_zbproposedc0p94";
  172. if (STI.hasFeature(RISCV::FeatureStdExtZbr))
  173. - Arch += "_zbr0p93";
  174. + Arch += "_zbr0p94";
  175. if (STI.hasFeature(RISCV::FeatureStdExtZbs))
  176. - Arch += "_zbs0p93";
  177. + Arch += "_zbs1p0";
  178. if (STI.hasFeature(RISCV::FeatureStdExtZbt))
  179. - Arch += "_zbt0p93";
  180. + Arch += "_zbt0p94";
  181. if (STI.hasFeature(RISCV::FeatureStdExtZvamo))
  182. Arch += "_zvamo0p10";
  183. if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
  184. diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
  185. index ae6c6b252d22..93f6acd53147 100644
  186. --- a/llvm/lib/Target/RISCV/RISCV.td
  187. +++ b/llvm/lib/Target/RISCV/RISCV.td
  188. @@ -148,13 +148,7 @@ def FeatureStdExtB
  189. [FeatureStdExtZba,
  190. FeatureStdExtZbb,
  191. FeatureStdExtZbc,
  192. - FeatureStdExtZbe,
  193. - FeatureStdExtZbf,
  194. - FeatureStdExtZbm,
  195. - FeatureStdExtZbp,
  196. - FeatureStdExtZbr,
  197. - FeatureStdExtZbs,
  198. - FeatureStdExtZbt]>;
  199. + FeatureStdExtZbs]>;
  200. def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
  201. AssemblerPredicate<(all_of FeatureStdExtB),
  202. "'B' (Bit Manipulation Instructions)">;
  203. --
  204. 2.33.1